Extreme ultraviolet lithography (EUVL) requires flare variation compensation technology and highly accurate critical dimension (CD) control for the fabrication of devices with feature sizes of 32 nm and beyond. To deal with these issues, a mask pattern suitable for evaluating flare and CD variation was designed based on the power spectral density (PSD) of the projection optics of the EUV1. The CD of the replicated patterns clearly varied with the local density of mask patterns, and the variation was affected by mask CD error and flare level. The impact of flare on CD variation was estimated very precisely (
Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be 6.1% or 6.6%, as calculated from the residual part of the low-or middle-frequency region, respectively. The flare level was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD, we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This research was supported in part by NEDO.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
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