Distribution system state estimation (DSSE) has been introduced to monitor distribution grids; however, due to the incorporation of distributed generations (DGs), traditional DSSE methods are not able to reveal the operational conditions of active distribution networks (ADNs). DSSE calculation depends heavily on real measurements from measurement devices in distribution networks. However, the accuracy of real measurements and DSSE results can be significantly affected by false data injection attacks (FDIAs). Conventional FDIA detection techniques are often unable to identify FDIAs into measurement data. In this study, a novel deep neural network approach is proposed to simultaneously perform DSSE calculation (i.e., regression) and FDIA detection (i.e., binary classification) using real measurements. In the proposed work, the classification nodes in the DNN allow us to identify which measurements on which phasor measurement unit (PMU), if any, were affected. In the proposed approach, we aim to show that the proposed method can perform DSSE calculation and identify FDIAs from the available measurements simultaneously with high accuracy. We compare our proposed method to the traditional approach of detecting FDIAs and performing SE calculations separately; moreover, DSSE results are compared with the weighted least square (WLS) algorithm, which is a common model-based method. The proposed method achieves better DSSE performance than the WLS method and the separate DSSE/FDIA method in presence of erroneous measurements; our method also executes faster than the other methods. The effectiveness of the proposed method is validated using two FDIA schemes in two case studies: one using a modified IEEE 33-bus distribution system without DGs, and the other using a modified IEEE 69-bus system with DGs. The results illustrated that the accuracy and F1-score of the proposed method are better than when performing binary classification only. The proposed method successfully detected the FDIAs on each PMU measurement. Moreover, the results of DSSE calculation from the proposed method has a better performance compared to the regression-only method, and the WLS methods in the presence of bad data.
System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for embedded real-time signal processing because of their high performance and low latency. Here we describe the process of implementing the Open Master Hearing Aid [1] on an SoC FPGA. We started by creating a FFT based Simulink model to implement hardware friendly frequency-domain processing. This model implements Short-Time Fourier Transform processing in an overlap-and-add architecture. This was followed by porting additional openMHA processing blocks, such as dynamic range compression, to Simulink. Once the hearing aid Simulink model was finished, Mathwork's HDL Coder was used to create VHDL. To create an interactive system, we used Audio Logic's code generation tools to generate the infrastructure needed to communicate with the hearing aid processor in real-time; this includes generating device drivers that allow Linux to communicate with the hearing aid processor, as well as a custom web application with an autogenerated GUI. This example provides an open reference design for those who may be interested in low latency FPGA based data flow architectures. 1. www.openmha.org
System-on-Chip (SoC) Field Programmable Gate Arrays (FPGAs) are ideal for real-time signal processing due to their low, deterministic latency and high performance. To showcase the utility of our open FPGA computational platform for real-time audio signal processing and computational modeling, several applications have been implemented. We have ported the openMHA hearing aid software [1] to our platform to show that pre-existing audio processing software can be implemented in SoC FPGAs by making external audio interfaces show up as a sound card. To highlight the ability to perform real-time computational modeling on our performance platform, we are implementing a real-time version of Laurel Carney’s auditory-nerve model [2] running in its own custom accelerator in the FPGA fabric. To illustrate the ability to develop DSP algorithms in MathWork’s Simulink and then implement them in the FPGA fabric we have taken several algorithms from Issa Panahi’s group [3] to show both frame-based processing (noise reduction) and sample-based processing (dynamic range compression). Finally, we show that the platform can be used to visualize audio signals using a real-time spectrogram where FFTs are computed in the FPGA fabric. [1] www.openmha.org. [2] JASA 126, 2390–2412. [3] www.utdallas.edu/ssprl/hearing-aid-project/.
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