Abstract| This paper describes new techniques for implementing a low-cost video decoder that can decode an HDTV bitstream and display the signal at lower resolutions. Two key algorithms are discusssed: downconversion and low-resolution motion compensation. In the proposed scheme, incoming blocks are subject to a down-conversion process within the decoding loop, hence motion compensation is performed from the downconverted images. The lters used for down-conversion are based on the concept of frequency synthesis, and the lters used to perform the low-resolution motion compensation are determined by an optimal least squares solution. Using these algorithms, three di erent architectures that provide equal quality with varying system level complexity are presented; the rst is directly derived from the initial model of low-resolution decoder, another attempts to reduce the amount of compuation for the IDCT, while another addresses the concerns regarding the amount of interface with an existing decoder structure. All of the above systems are hierarchical with regard to the logic used for ltering and scalable in the amount of memory which is required to reconstruct each output layer. Our simulation results demonstrate that high quality video can be provided at lower-resolutions with signi cant memory savings.
The purpose of this paper is to investigate the possible means of down converting an incoming HDTV signal into one which is suitable for display onto an NTSC monitor. We present a novel frequency synthesis algorithm which constructs a set of 8x8 DCT coefficients from four original 8x8 DCT blocks. Also, a down-conversion decoder employing a unique adaptive motion compensation algorithm is presented. Using this fixed motion compensation algorithm, the proposed down-conversion technique is compared to the conventional method. Both yield acceptable image sequences with different trade-offs in complexity and quality.
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