An excellent 64Mb chainFeRAM TM using a highly reliable capacitor with damage-robust MOCVD-PZT and SrRuO 3 /IrO 2 top electrode (TE) is successfully demonstrated for the first time. A very large signal margin of 540mV at 1.8V is achieved for the capacitor as small as 0.19µm 2 . Large sensing margin is well maintained after 85°C storage, and 10 years lifetime is successfully guaranteed. The combination of damage-robust MOCVD-PZT and optimized SrRuO 3 /IrO 2 TE as well as a sophisticated 'chain' structure that has a small bit line capacitance (Cb) nature shows excellent reliability and scalability. This work demonstrates that high density 256Mb chain FeRAM with 0.1µm 2 planar capacitor can be realized.
This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both "1" and "0" data. The reference bitline bias of 64 Mb chip is designed to keep intermediate value of "1" and "0" data at any operating temperatures from C to 85 C by introducing a modified band-gap reference circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by 22 mV. Moreover, a new reference bias circuit called the "elevator circuit" with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array operating voltage VAA fluctuation as well as temperature variation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by 40 mV. The elevator circuit also varies reference bitline bias with array operating voltage VAA variation, resulting in improvement of cell signal windows by 44 mV in the range of 1.5 V 0.2 V VAA.
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