Abstract-At low GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160nm CMOS chip with maximum delay of 550psec is demonstrated with monotonous delay steps of 13 psec (41 steps) and an RMS delay variation error of less than 10psec over more than an octave in frequency (1 -2.5GHz). The delay per area is at least 50x more than for earlier chips. The allpass cells are used to realize a four element timed array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed array IC-architecture.

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ICD group/Carré building7500 AE Enschede/The Netherlands Electronically variable delays for beamforming are generally realized by phase shifters. Although a constant phase shift can approximate a time-delay in a limited frequency band, this does not hold for larger arrays that scan over wide angles and have a large instantaneous bandwidth. In this case true time-delays are wanted to avoid effects such as beam-squinting. In this paper we aim at compactly integrating a delay based phased array receiver in standard CMOS IC-technology. This is for instance relevant for synthetic aperture radars, which require large instantaneous bandwidths often in excess of 1 GHz, either as RF or as IF-bandwidth in a super-heterodyne system. We target low-GHz radar frequencies, assuming sub-arrays of four elements and up to 550 psec delay.Integrated time-delay cells have been proposed based on the approximation of transmission line segments with integrated LC lumped elements [1]. These, however, require bulky on-chip inductors. A gm-RC or gm-C all-pass delay circuit [2,3] can produce a given amount of delay in a much smaller area. This paper proposes an improved gm-C delay cell that realizes an accurate

All-pass filter circuits can implement a time delay but, in practice, show delay and gain variations versus frequency, limiting their useful frequency range. This brief derives analytical equations to estimate this frequency range, given a certain maximum allowable budget for variation in delay and gain. We analyze and compare two well-known g m − RC first-order allpass circuits, which can be compactly realized in CMOS technology and relate their delay variation to the main pole frequency. Modeling parasitic poles and putting a constraint on gain variation, equations for the maximum achievable pole frequency and delay variation versus frequency are derived. These equations are compared with simulation and used to design and compare delay cells satisfying given design goals.

This paper shows that the group delay of a delay circuit does not give sufficient information to predict the delay vs. frequency. A new criterion (f ϕ=0) is proposed that characterizes the delay variations over a specified frequency range. The mathematical derivation of f ϕ=0 for a single delay block and a cascade of delay blocks is shown. As examples the criterion is applied to the design of an RC and LC delay block. Delay predictions based on f ϕ=0 are compared with simulation results, showing reasonable agreement. I.