No abstract

No abstract

This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K 2 2 2 16-b SRAM fabricated in a 0.25-m dual-Vt Vt Vt CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes.

Quantum feedback control protocols can improve the operation of quantum devices. Here we examine the performance of a purification protocol when there are imperfections in the controls. The ideal feedback protocol produces an x-eigenstate from a mixed state in the minimum time, and is known as rapid state preparation. The imperfections we examine include time delays in the feedback loop, finite strength feedback, calibration errors and inefficient detection. We analyse these imperfections using the Wiseman-Milburn feedback master equation and related formalism. We find that the protocol is most sensitive to time delays in the feedback loop. For systems with slow dynamics, however, our analysis suggests that inefficient detection would be the bigger problem. We also show how system imperfections, such as dephasing and damping, can be included in a model via the feedback master equation.

No abstract