It has recently been suggested that the thin degenerate layer found at the GaN/sapphire interface results from a high concentration of stacking faults. The studies of this letter, however, show that this is not the most likely explanation for the presence of such a degenerate layer. Using x-ray energy-dispersive spectroscopy and secondary ion-mass spectroscopy, profile distributions of elements Ga, N, O, C, and Al, near the interface, have been obtained. The distributions reveal very high O and Al concentrations in the GaN film within 0.2 m from the interface, together with a material depletion of Ga and N. Such conditions strongly favor n ϩ conductivity in this interfacial region because not only are N-vacancy and N-site O donors present, but Al incorporated on the Ga sublattice reduces the concentration of compensating Ga-vacancy acceptors. The two-layer ͑film plus interface͒ conduction has been modeled, and the effect of conduction in the GaN film thus isolated.

This paper presents the frequency and output power characteristics of oscillators in the graphene tunneling FETs (GTFET) technology. In order to acquire these characteristics, the practical operating conditions of GTFET oscillators are carefully analyzed, and then, the device parameters are simplified to an equivalent circuit and the I/V large signal model is approximated by a compact form. Expressions for the maximum oscillation frequency, maximum output power, and the relationship between frequency and power are given combing the equivalent circuit and the simplified model. In addition, the key device parameters that can be used to improve the performance of a GTFET oscillator are also discussed.

2D van der Waals (vdW) semiconductors hold great potentials for more‐than‐Moore field‐effect transistors (FETs), and the efficient utilization of their theoretical performance requires compatible high‐k dielectrics to guarantee the high gate coupling efficiency. The deposition of traditional high‐k dielectric oxide films on 2D materials usually generates interface concerns, thereby causing the carrier scattering and degeneration of device performance. Here, utilizing a space‐confined epitaxy growth approach, the authors successfully obtained air‐stable ultrathin indium phosphorus sulfide (In2P3S9) nanosheets, the thickness of which can be scaled down to monolayer limit (≈0.69 nm) due to its layered structure. 2D In2P3S9 exhibits excellent insulating properties, with a high dielectric constant (≈24) and large breakdown voltage (≈8.1 MV cm−1) at room temperature. Serving as gate insulator, ultrathin In2P3S9 nanosheet can be integrated into MoS2 FETs with high‐quality dielectric/semiconductor interface, thus providing a competitive electrical performance of device with subthreshold swings (SS) down to 88 mV dec−1 and a high ON/OFF ratio of 105. This study proves an important strategy to prepare 2D vdW high‐k dielectrics, and greatly facilitates the ongoing research of 2D materials for functional electronics.

CdO : Ag nanocomposites with metallic Ag nanoparticles embedded in the polycrystalline CdO matrix were synthesized by the solid-state reaction method. The addition of Ag led to increased grain boundaries of CdO and created numerous CdO/Ag interfaces. By incorporating Ag into the CdO matrix, the power factor was increased which was probably due to the carrier energy filtering effect induced by the enhanced energy-dependent scattering of electrons. In addition, reduced thermal conductivity was also achieved by stronger phonon scattering from grain boundaries, CdO/Ag interfaces and Ag nanoparticles. These concomitant effects resulted in enhanced ZT values for all CdO : Ag nanocomposites, demonstrating that the strategy of introducing metallic Ag nanoparticles into the CdO host was very effective in optimizing the thermoelectric performance.