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A fabrication process for Nb/Al-AlO x /Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO 2 interlayer dielectric. JJ electric properties and statistics such as onchip and wafer spreads of critical current, I c , normal-state conductance, G N , and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, J c , from 10 kA/cm 2 to 50 kA/cm 2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The G N and I c spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. I c and G N spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10 6 JJ/cm 2 and 193-nm photolithography for JJ definition are discussed. Index Terms-Nb/Al-AlO x /Nb Josephson junctions, RSFQ, RQL, superconducting integrated circuit, superconductor electronics, self-shunted junction, 248-nm photolithography, minimum printable size, mask error enhancement function S 2EPo1A-02

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