The surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing long-term mechanical stress and the influence of stress on electrical characteristics. Our simulated results show that the nonuniform stress in the gate insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a nonuniform degradation phenomenon, which affects both the performance and the reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the subchannel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with the lowest protrusions demonstrates the smallest degradation after undergoing long-term bending.
A low-temperature method, supercritical CO 2 ͑SCCO 2 ͒ fluid technology, is employed to improve the device properties of ZnO TFT at 150°C. In this work, the undoped ZnO films were deposited by sputter at room temperature and treated by SCCO 2 fluid which is mixed with 5 ml pure H 2 O. After SCCO 2 treatment, the on/off current ratios and threshold voltage of the device were improved significantly. From x-ray photoelectron spectroscopy analyses, the enhancements were attributed to the stronger Zn-O bonds, the hydrogen-related donors, and the reduction in dangling bonds at the grain boundary by OH passivation.
This paper investigates anomalous capacitance-voltage (C-V) degradation in amorphous indium-gallium-zinc-oxide (a-IGZO) thinfilm-transistors (TFTs) under hot carrier stress. In vacuum hot carrier stress, both the gate-to-drain capacitance (C GD ) and the gateto-source capacitance (C GS ) curves exhibited positive shifts due to electron trapping in the gate dielectric. In addition, an observed increase in capacitance value at a lower gate voltage in the C GD measurement only can be ascribed to interface state creation. However, when the hot carrier stress was performed in an oxygen-rich environment, the C GD -V G curve showed a significantly positive shift due to the electric-field-induced oxygen adsorption near the drain terminal. The degradation in the C GS -V G curve is due not only to the positive shift, but also the anomalous two step turn-on behavior. This phenomenon can be ascribed to the electron trapping in the gate dielectric and electric-field-induced oxygen adsorption on the channel layer, especially in the area adjacent to the drain terminal. The electron trapping increased the source energy barrier, with the electric-field-induced oxygen adsorption further raising the energy-band near the drain, resulting in a two-step turn-on behavior in the C GS -V G curve.
The composition of buffer layer would be played a key role to affect the electrical performance and the reliability of the selfaligned top-gate a-IGZO TFTs. In this work, the threshold voltage shift (ΔVth) of the device could be less than ±1V under positive and negative bias thermal illumination stress.
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