Seizures are the manifestation of highly synchronized burst firing of a large population of cortical neurons. Epileptiform bursts with an underlying plateau potential in neurons are a cellular correlate of seizures. Emerging evidence suggests that the plateau potential is mediated by neuronal canonical transient receptor potential (TRPC) channels composed of members of the TRPC1/4/5 subgroup. We previously showed that TRPC1/4 double-knockout (DKO) mice lack epileptiform bursting in lateral septal neurons and exhibit reduced seizure-induced neuronal cell death, but surprisingly have unaltered pilocarpine-induced seizures. Here, we report that TRPC5 knockout (KO) mice exhibit both significantly reduced seizures and minimal seizure-induced neuronal cell death in the hippocampus. Interestingly, epileptiform bursting induced by agonists for metabotropic glutamate receptors in the hippocampal CA1 area is unaltered in TRPC5 KO mice, but is abolished in TRPC1 KO and TRPC1/4 DKO mice. In contrast, long-term potentiation is greatly reduced in TRPC5 KO mice, but is normal in TRPC1 KO and TRPC1/4 DKO mice. The distinct changes from these knockouts suggest that TRPC5 and TRPC1/4 contribute to seizure and excitotoxicity by distinct cellular mechanisms. Furthermore, the reduced seizure and excitotoxicity and normal spatial learning exhibited in TRPC5 KO mice suggest that TRPC5 is a promising novel molecular target for new therapy.

Hardware and compiler techniques for mapping data-parallel programs with divergent control flow to SIMD architectures have recently enabled the emergence of new GPGPU programming models such as CUDA, OpenCL, and DirectX Compute. The impact of branch divergence can be quite different depending upon whether the program's control flow is structured or unstructured. In this paper, we show that unstructured control flow occurs frequently in applications and can lead to significant code expansion when executed using existing approaches for handling branch divergence.This paper proposes a new technique for automatically mapping arbitrary control flow onto SIMD processors that relies on a concept of a Thread Frontier, which is a bounded region of the program containing all threads that have branched away from the current warp. This technique is evaluated on a GPU emulator configured to model i) a commodity GPU (Intel Sandybridge), and ii) custom hardware support not realized in current GPU architectures. It is shown that this new technique performs identically to the best existing method for structured control flow, and re-converges at the earliest possible point when executing unstructured control flow. This leads to i) between 1.5 − 633.2% reductions in dynamic instruction counts for several real applications, ii) simplification of the compilation process, and iii) ability to efficiently add high level unstructured programming constructs (e.g., exceptions) to existing data-parallel languages.