Interposer technologies offer high density, high performance interconnects for integrated systems resulting in smaller form factors and improved system performance as compared to traditional packages. This paper sheds light on the different design tradeoffs which result from the usage of silicon and glass interposers due to the different material characteristics. The emphasis is on the redistribution layers (RDLs) of the interposer rather than the through silicon vias (TSVs) due to the long length of these wires. Guidelines of designing the interconnects for different design objectives on silicon and glass interposers are presented. Interconnects on glass interposers are more efficient in terms of power dissipation and delay. Conversely, wires on glass interposers suffer from twice as high crosstalk as compared to silicon at minimum pitch. Interconnects on glass interposers exhibit 35% better power-delay product (PDP) than on silicon for fixed pitch at 1.95 µm. More importantly, minimum pitch does not result in minimum delay, power dissipation, and crosstalk. The interconnect design parameters that satisfy these objectives under different constraints are different for the two materials. Consequently, the various tradeoffs between area and noise as well as power and delay must be considered in the design process.
In the era of post-device scaling, three-dimensional (3-D) integration is a promising solution to meet performance, power, and cost requirements in modern applications, such as IoT, high performance computing, and cyber-physical systems. A novel design automation flow, compatible with static timing analysis (STA), for exploring the timing and power of 3-D ICs is proposed. Among the different types of vertical interconnects, TSVs modeled as RC wires, are considered in this work. The flow enables design space exploration and optimization utilizing existing timing and power analysis tools, e.g. PrimeTime and PrimeTimePX. The design experience is similar to a 2-D design flow where the placement in multiple tiers is merely performed by an open-source 3-D placer. Application of the flow to different benchmark circuits shows that even with no optimization effort, a two tier 3-D stack produced by the flow achieves up to 14.6% average power reduction, 18.7% performance improvement, and 49% footprint reduction as compared to the 2-D design for a specific circuit 1 .
Multi-level voltage scaling is one of the most effective techniques for reducing power without sacrificing speed in an integrated circuit (IC). However, additional circuitry is required at the interfaces of the circuit blocks which operate at different voltage levels. These circuits impose a significant delay overhead and restrict the use of multi-voltage scaling at blocks where critical paths traverse their interfaces. A bypass circuit is proposed to alleviate these timing issues under specific operation conditions. The new circuit results in significant performance improvements of up to 89% and power reduction up to 52% compared to a traditional feedback-based level-up shifter in a 32 nm technology node. Furthermore, greater performance and power savings are demonstrated when more cells are being bypassed, such as the isolation cells.
Thermal analysis is a high performance computing problem because the microscale spatial and time discretization of the heat equation translates into repeatedly solving large linear systems of equations. In previous works, compact models of integrated circuits (IC) were introduced to speed up this process. However, such methods are limited in their accuracy as they approximate the underlying physics. The solution methodologies for such models are also ill-suited to simulate the thermal characteristics of an IC at cell-level. The finite element method (FEM) is an appropriate computational technique for providing both fast and accurate thermal analyses. Considering that the number of cells in modern ICs is in the order of millions, thermal analysis at this abstraction level is a formidable task. Consequently, handling the computational meshes and computing thermal profiles of an IC at the cell-level requires intensive computing power. In order to provide accurate cell-level thermal simulations at a lower computational cost, this work introduces an advanced mesh generator for cell-level floorplans. This mesh generator applies a cell-homogenization technique based on the initial cell-level floorplan and the power trace to create reduced order meshes for e cient cell-level thermal simulations. The e↵ects of using di↵erent homogenization algorithms are explored to illustrate the tradeo↵ between the simulation speed and the solution accuracy. Results show that the proposed technique can achieve a 90% reduction in the number of nodes in the mesh with less than 5% error to the temperature of the full scale mesh. In addition, the simulation time is reduced by an order of magnitude.
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