This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent 1996 IEEE International Solid-state Circuits Conference 0-7803-3136-2 I 96 I $5.00 I 0 lEEE

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This paper describes the clock distribution and synchronization network for a 64 bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter 1 ps and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves 0.8 ps/mV rms and 9 ps of period jitter and skew, respectively. By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitude and thus is suited for high speed synchronization operations, is proposed.