The wafer-scale integration of the downscaled devices such as transistors based on two-dimensional (2D) transition metal dichalcogenide (TMD) has attracted great attention in recent years. Such integration is also a significant step towards the system-level application of these novel lowdimensional semiconductors. Yet, so far, functional logic circuits based on the 2D TMDs have rarely been reported, largely because of the absence of an effective approach for large-scale TMD synthesis and the unsatisfactory elementary logic cell performance. In this work, n-type inverter (NOT gate circuit) arrays have been fabricated based on a wafer-scale 2D molybdenum disulfide (MoS 2 ) thin film which is grown by atomic layer deposition (ALD). High-quality crystallinity and excellent wafer-level uniformity have been successfully achieved. The n-type inverter array exhibits a fast response with 50 Hz inverse-frequency. The impact of the device geometry on the inverter performance has also been characterized by designing various width ratio between the load and pull-down transistors. These results open up an attractive approach to realize the practical application of wafer-scale 2D MoS 2 in logic and circuit systems.Nanoelectronic devices built on two-dimensional (2D) materials, such as semiconducting transition metal dichalcogenides (TMDs), [1][2][3] silicene, [4] black phosphorus, [5] and so forth are considered as promising candidates for the next-generation high-mobility and low-power electronics which is currently dominated by low-mobility amorphous silicon. [6] MoS 2 , a typical TMD semiconductor, has been widely studied due to its unique material properties and promising applications in various fields including photonics, [7][8][9] sensing, [10] field-effect transistor (FET)based nanoelectronics, [2,[11][12][13] and so on. As compared with conventional Si material in an ultra-scaled FET, the 2D MoS 2 can enable excellent electro-static gate control suppressing shortchannel effects while maintaining good semiconductor features and decent mobility. [14,15] Although the researches focusing on TMD materials and devices have been emerging in a large quantity since the first report on MoS 2 FET in 2011, [2] the circuit-level applications have been bottlenecked for a long time by the limited approaches to effectively prepare high-quality and large-area TMD thin films. Lately, a complementary MoS 2 inverter based on fin-shaped structure has been reported by using ion implantation to form p-type MoS 2 , which however is not highly reproducible to fabricate largearea and high-quality TMD thin films. [16]
Wafer-scale synthesis of p-type TMD films is critical for its commercialization in next-generation electro/optoelectronics. In this work, wafer-scale intrinsic n-type WS2 films and in situ Nb-doped p-type WS2 films were synthesized through atomic layer deposition (ALD) on 8-inch α-Al2O3/Si wafers, 2-inch sapphire, and 1 cm2 GaN substrate pieces. The Nb doping concentration was precisely controlled by altering cycle number of Nb precursor and activated by postannealing. WS2 n-FETs and Nb-doped p-FETs with different Nb concentrations have been fabricated using CMOS-compatible processes. X-ray photoelectron spectroscopy, Raman spectroscopy, and Hall measurements confirmed the effective substitutional doping with Nb. The on/off ratio and electron mobility of WS2 n-FET are as high as 105 and 6.85 cm2 V-1 s-1, respectively. In WS2 p-FET with 15-cycle Nb doping, the on/off ratio and hole mobility are 10 and 0.016 cm2 V-1 s-1, respectively. The p-n structure based on n- and p- type WS2 films was proved with a 104 rectifying ratio. The realization of controllable in situ Nb-doped WS2 films paved a way for fabricating wafer-scale complementary WS2 FETs.
In this paper the annealing effects in N 2 on the electrical characteristics of a TiN/HfO 2 /GeON/p-Ge capacitor are investigated. Well behaved capacitance-voltage curves were obtained for the sample annealed at 400 • C for 3 min in N 2 . A negligible hysteresis was demonstrated comparing with a hysteresis of 0.5 V for the as-deposited sample. The suppression of hysteresis is attributed to the reduction of electron traps in the dielectric layer, which is verified by the MOS pulse method. Besides, the interface states' density is also greatly reduced by annealing in N 2 and confirmed by the conductance method.
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