In this paper, two types (i.e., type-A and type-B) of hybrid microstrip/defected ground structure (DGS) cells are proposed for passive circuit implementation with ultra-wide stopband. Both cells consist of the stepped-impedance DGS and embedded folded slotline on the ground, which could obtain the dual-resonances. In type-A cell, a microstrip T-stub on the top side is introduced, which can not only allocate a strong coupling to the DGS with slotline on the bottom side, but also act as the input/output port. To finely adjust the dual-resonances of the type-B cell, a grounded microstrip patch is used. Meanwhile, such compact cells could feature an ultra-wide upper stopband, due to their own slow-wave effect. Based on the aforementioned hybrid microstrip/DGS cells, two dual-band bandpass filters (BPFs) and a dual-band filtering power divider (FPD) are proposed and fabricated. Measured and simulated results are in a fairlyclose agreement. Both dual-band BPFs exhibit the ultra-wide upper stopband, which extends up to 40 GHz with a high rejection level about 30 dB. Besides, the dual-band FPD has merits of more than 18.7 dB of in-band isolation and 28 dB stopband rejection levels up to 40 GHz. INDEX TERMS Bandpass filter (BPF), defected ground structure (DGS), dual-band filter, filtering power divider (FPD), slow-wave, ultra-wide stopband.

A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting (HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the complex domain. Less power-combining ways and dc power supplies are required for proposed PA comparing to previously reported works with deep PBO efficiency enhancement. A reconfigurable matching network (RMN) based on a novel reconfigurable transformer is proposed with more freedom to achieve a flexible load impedance tuning range of the sub-PAs. The characteristics of the reconfigurable transformer based on tunable inductors are analyzed. Efficiency enhancement is achieved at 3-/6-/9-/12-/15-dB PBOs without any supply switching or PA short-switches. The PA is fabricated in 40-nm CMOS technology with a core size of 0.83 mm 2 . Operating at 2.3-3.4 GHz, it introduces 24.2-dBm peak P out with 38.5% peak drain efficiency (DE) at 2.8 GHz. It achieves 38.5%/29.6%/18.4% at 2.8 GHz and 34.7%/26.6%/17.8% DE at 3.3 GHz for 0-/6-/12-dB PBO, 39.3%/29.5%/14.9% at 2.8 GHz, and 35.3%/27.9%/15.9% DE at 3.3 GHz for 3-/9-/15-dB PBO, respectively. For 10-MHz 256-QAM modulation signal, it delivers 16.22-/15.50-dBm average P out with EVM of −32.3/−33.0 dB, average DE of 24.6%/22.7%, and ACLR of −33.20/−31.54 dBc at 2.8/3.3 GHz, respectively. For 20-MHz 64 QAM modulation signal, it exhibits 16.42-/15.52-dBm average P out with EVM of −29.1/−29.3 dB, average DE of 24.9%/22.78%, and ACLR of −30.78/−30.74 dBc at 2.8/3.3 GHz, respectively.

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This article presents a quadrature switched/floated capacitor power amplifier (SFCPA) with deep back-off efficiency enhancement. The SFCPA is introduced to decrease the dynamic power consumption at power back-off (PBO), which could improve the system efficiency (SE). The reconfigurable self-coupling canceling transformer (RSCCT) with enhanced tuning range of turn ratio is used to achieve impedance boosting for further improved efficiency at deep PBO. Based on the proposed SFCPA, a watt-level quadrature digital power amplifier (DPA) with IQ cell sharing, hybrid Doherty, and impedance boosting is proposed for deep PBO efficiency enhancement. Implemented in 40-nm CMOS, the proposed DPA with 1.2-/2.4-V supply achieves 30.3-dBm saturated output power ( P out ) with 36.6%/32.9%/29.1%/23.7%/18.6%/13.2% SE for 0-/3-/6-/9-/12-/15-dB PBOs at 2.4 GHz. For 60-MHz 256-QAM modulation signal, it delivers 23.32-dBm average output power ( P avg ) with an error vector magnitude (EVM) of −31.9 dB and an average drain efficiency (DE) of 30.7%. For 40-MHz 1024-QAM signal, it shows 20.44-dBm P avg with an EVM of −35.9 dB and an average DE of 22.6%.

A novel architecture of a digital modulated polar phased-array transmitter with phase modulation (PM) phase-shifting and feed-forward controlled dynamic matching (FFCDM) is presented in this article. Phase-shifting in a PM signal path is utilized in each element, which shares many components including a phase modulator, baseband, and IF components. The characteristics of the proposed architecture are analyzed. With a constant envelope of PM signals, the implicit nonlinearity of the phase shifter in this architecture has low impact on the linearity performance of a phased-array system. Meanwhile, low phase error can be achieved by high-resolution phase interpolation with the digital predistortion (DPD) technique. Efficiency for both saturated and 6-dB back-off power is enhanced by digital power amplifier (DPA) with FFCDM. As a proof of concept, a 3-7 GHz 4-element phased-array transmitter is designed and fabricated in 40-nm CMOS based on the proposed method. The measured root-mean-square (rms) phase error of 0.3 • , effective phase shifting resolution of 9-bit, and peak system efficiency of 38.2% are achieved. For 40 MHz 64-QAM modulation signal, it exhibits EVM of 5.38% and 5.37%, P out of 14.30 and 14.46 dBm, and PAPR of 7.08 and 6.97 at 3.5 and 5.2 GHz, respectively. The measured peak EIRP is 35.6 dBm with a unit antenna gain of 2.98 dBi at 5 GHz. The radiation patterns with 0 • , 15 • , 30 • , and 45 • steering are measured based on monopole antennas. Meanwhile, the array achieves <4.7% and <5.9% EVM for 64-QAM signals with bandwidths of 20 and 40 MHz, respectively.

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