manufacturable, high throughput process. Currently, In this paper, we present the latest advancements 75 mm diameter InP substrates are used and EBL of sub 50 nm InGaAs/InAlAs/InP High Electron lithography requires less than 1 hour for exposure Mobility Transistor (InP HEMT) devices that have over the wafer. A maximum wafer throughput of 150 achieved extrapolated Fmax above 1 THz. This wafers per week and 100 wafers per week on 100 mm extrapolation is both based on unilateral gain (1.2 diameter wafers would be possible on a single EBL THz) and maximum stable gain/maximum available system. A 2nd key enhancement is the reduction of gain (1.1 THz) extrapolations, with an associated fT of ohmic contact resistance through a higher doped cap 385 GHz. This extrapolation is validated by the layer design coupled with a InAs/InGaAs channel demonstration of a 3-stage common source low noise grown by molecular beam epitaxy. The sheet MMIC amplifier which exhibits greater than 18 dB gain resistance of the epitaxial layers is lowered to 75 at 300 GHz and 15 dB gain at 340 GHz. ohm/sq. (compared to 110 ohm/sq. in the baseline InP HEMT profile) and the mobility was improved to as INTRODUCTION high as 15,000 cmA2N-sec (compared to 12,000 Future systems will extend the need for higher cmA2/V-sec in the baseline InP HEMT profile). A low frequency and bandwidth devices and circuits beyond contact resistance of 0.05 ohm-mm and a high peak current capability and concepts. Rapid development transconductance as high as 2300 mS/mm was and advancement of solid state transistor and MMIC measured at 1V drain bias with a device breakdown technology has pushed extremely high cutoff typically of 2.5V and a maximum drain source voltage frequency and high maximum oscillation frequencies of 2V and good device pinchoff characteristics. (Fmax) in various technologies [1][2][3]. This paper describes the latest advancements of sub 50 nm InP HEMT DEVICE MEASUREMENTS InGaAs/InAlAs/InP High Electron Mobility Transistor S-parameter measurements on extended (InP HEMT) devices that have achieved extrapolated reference plane 2 finger 20 um grounded CPW Fmax above 1 THz for the first time to the best of our devices with 2-mil thick substrates were measured knowledge and is validated by the demonstration of a from 1-110 GHz. The grounded CPW and extended 3-stage low noise MMIC amplifier at 340 GHz with reference plane serve to reduce measurement and greater than 15 dB gain. calibration issues such as probe coupling and substrate modes. The device performance is deInP HEMT DEVICE FABRICATION embedded using an EM simulated SOLT calibration To develop the THz Fmax InP HEMT device, structures fabricated on-wafer. H21 and maximum several process enhancements were implemented on stable gain (MSG) are relatively smooth and follows NGST's baseline InP HEMTs [4]. One key process the theoretical slope of -20 dB/decade and -10 enhancement was the reduction of gate length from dB/decade slope closely from 1 -110 GHz. The 70 to less than 50 nm. Based on cross sections ext...

Macroscopic resonant tunneling between the two lowest lying states of a bistable rf SQUID is used to characterize noise in a flux qubit. Measurements of the incoherent decay rate as a function of flux bias revealed a Gaussian-shaped profile that is not peaked at the resonance point but is shifted to a bias at which the initial well is higher than the target well. The rms amplitude of the noise, which is proportional to the dephasing rate 1/tauphi, was observed to be weakly dependent on temperature below 70 mK. Analysis of these results indicates that the dominant source of low energy flux noise in this device is a quantum mechanical environment in thermal equilibrium.

A general method for directly measuring the low-frequency flux noise (below 10 Hz) in compound Josephson junction superconducting flux qubits has been used to study a series of 85 devices of varying design. The variation in flux noise across sets of qubits with identical designs was observed to be small. However, the levels of flux noise systematically varied between qubit designs with strong dependence upon qubit wiring length and wiring width. Furthermore, qubits fabricated above a superconducting ground plane yielded lower noise than qubits without such a layer. These results support the hypothesis that localized magnetic impurities in the vicinity of the qubit wiring are a key source of low frequency flux noise in superconducting devices.Qubits implemented in superconducting integrated circuits show considerable promise as building blocks of scalable quantum processors. However, low frequency noise in superconducting devices places fundamental limitations on their use in quantum information processing [1,2,3,4]. Recent theoretical work has highlighted several potential sources for low frequency noise. These include ensembles of two level systems (TLS) that could be associated with dielectric defects [5,6,7], magnetic impurities in surface oxides on superconducting wiring [8] and flux noise induced by spin flips at dielectric interfaces [9]. Characterizing low frequency noise is an essential step in understanding its mechanism and in developing fabrication strategies to minimize its amplitude. Several techniques have been exploited to indirectly measure low frequency noise in superconducting qubits [10,11]. This article describes a technique for directly measuring low frequency noise in RF-SQUID flux qubits. We present measurements performed on a series of qubits of varying wiring lengths and widths and qubits with and without superconducting shielding layers.The devices described in this paper were fabricated on an oxidized Si wafer with a Nb/Al/Al 2 O 3 /Nb trilayer process. There were two additional wiring layers, WIRA, and WIRB, above the trilayer (see Fig 1a). All wiring layers were insulated from each other with layers of sputtered SiO 2 . Eighty-five qubits with a range of geometries (wiring length, wiring width, and the presence or absence of shielding planes) were tested. Qubit wiring lengths ranged from 350 µm to 2.1 mm and wiring widths ranged from 1.4 µm to 3.5 µm. Moreover, the qubits were drawn from several wafers to control for variability in fabrication process conditions.The compound Josephson junction (CJJ) RF-SQUID is shown schematically in Fig. 1b and consists the Hamiltonian for an isolated device can be approximately expressed as [12]:where Φ q is the total flux, Q is the charge stored in the net capacitance C q across the junctions, E J = Φ 0 I q c /2π and Φ 0 = h/2e. The potential energy U (Φ q ) is monostable when β = 2πL q I c cos(πΦ cjj x /Φ 0 )/Φ 0 < 1 and classically bistable, with two counter-circulating persistent current states (denoted as |0 and |1 ) possessing persistent cur...

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