Spur-Free Fractional-N PLL Utilizing Precision Frequency and Phase Selection

Abstract

An architecture for fractional-N frequency synthesis is presented. The proposed topology does not use the traditional method of obtaining the fractional division via an average of N and N+1 divided clock cycles. Instead, it uses the equally spaced phases provided from a ring oscillator that works as VCO to generate the fractional frequency. Therefore, the proposed architecture does not generate any spurs due to fractional frequency synthesis. As a result it provides better resolution for the fraction and avoids any compensation required for correction of the instantaneous jitter.

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

“…The proposed architecture is dedicated for FDSOI technology using back-gate biasing opportunity to reduce the phase noise. The FPD PLL architecture [7] produces no fractional division error, and that is energy-saving because it allows fractional-N PLL without sigma-delta, time-todigital converter, or other averaging technique.…”

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

“…The proposed architecture is dedicated for FDSOI technology using back-gate biasing opportunity to reduce the phase noise. The FPD PLL architecture [7] produces no fractional division error, and that is energy-saving because it allows fractional-N PLL without sigma-delta, time-todigital converter, or other averaging technique.…”

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

“…The proposed architecture is dedicated for FDSOI technology using back-gate biasing opportunity to reduce the phase noise. The FPD PLL architecture [7] produces no fractional division error, and that is energy-saving because it allows fractional-N PLL without sigma-delta, time-todigital converter, or other averaging technique.…”

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

“…The proposed architecture is dedicated for FDSOI technology using back-gate biasing opportunity to reduce the phase noise. The FPD PLL architecture [7] produces no fractional division error, and that is energy-saving because it allows fractional-N PLL without sigma-delta, time-todigital converter, or other averaging technique.…”