Yield and Reliability of Cu Capped with CoWP using a Self-Activated Process

Gambino, J.; Wynne, J.; Gill, Jason M.R.; Mongeon, S.; Meatyard, D.; Bamnolker, H.; Hall, L.; Li, N.; Hernández, Marianella; Little, Penelope; Hamed, Mohammed S. G.; Иванов, Игорь Анатольевич

doi:10.1109/iitc.2006.1648637

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…The vias in the interconnect stack have the highest reliability concerns [23], [24], [25], [26], [27] and incorporating regularity at the lower levels of abstraction shows clear benefits with the UR implementations using the lowest number of vias as is evident from Fig. 2b.…”

Section: A Raw Implementation Metricsmentioning

confidence: 95%

Manufacturable nanometer designs using standard cells with regular layout

Subramaniyan

Larsson-Edefors

2013

International Symposium on Quality Electronic Design (ISQED)

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Abstract-In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS'89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.

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Section: A Raw Implementation Metricsmentioning

confidence: 95%

Manufacturable nanometer designs using standard cells with regular layout

Subramaniyan

Larsson-Edefors

2013

International Symposium on Quality Electronic Design (ISQED)

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“…Most voids are commonly generated at the interface between a top of Cu line and an upper capping dielectric due to the lowest activation energy for Cu diffusion (0.9eV). Thus, a number of studies have been published that selective deposition of thin metal on Cu lines can prevent this movement [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Formation of highly reliable Cu/low-k interconnects by using CVD Co barrier in dual damascene structures

Jung

Lee

Tsukasa

et al. 2011

2011 International Reliability Physics Symposium

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CVD Co film was investigated as an alternative barrier layer to the conventional PVD TaN\Ta in V1\M2 structure for 32nm node. We improved via filling performance and upstream (V1→M2) electromigration (EM) lifetime by more than three times. Excellent step coverage of CVD barrier makes it possible to reduce the thickness of the barrier metal by 30% and to increase the volume of Cu in metal lines. RC delay also reduced with decrease in resistance. Since adhesion at the interface between the barrier-Co and Cu also is strong, migration of Cu atoms is dramatically slowed down. EM in the via is finally deterred due to absence of pre-existing voids, consequently lifetime increases. This CVD Co process is expected to be beneficial for the next technology generation beyond 20nm node.

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Enhanced Grain Growth of Electroplated Copper on Cobalt-Containing Seed Layer

Huang

Baker-O'Neal

Cabral

et al. 2013

J. Electrochem. Soc.

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Cu films with low impurities were electroplated on pure Cu, CuCo alloy and electrodeposited Co seed layers to study the room temperature grain growth behavior. As-evaporated Cu and CuCo alloy seed layers showed a significant enhancement effect on the Cu recrystallization compared with sputtered Cu seed layers and post-annealed evaporated seed layers. The impact of the electrodeposited Co seed layer on the Cu grain growth was found to be dependent on the Co plating chemistry and on the thickness of the Co film. Co films plated in the absence and presence of saccharin showed a crystal structure of fcc and hcp, respectively. While the former showed little to no impact on the Cu recrystallization, the later was found to enhance or hinder the Cu recrystallization depending on the thickness of the Co. Studies on a Cu/Co sandwich stack structure showed that the recrystallization started at the top Cu layer, proceeding to the middle layer and then to the bottom layer.

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Yield and Reliability of Cu Capped with CoWP using a Self-Activated Process

Cited by 3 publications

References 5 publications

Manufacturable nanometer designs using standard cells with regular layout

Manufacturable nanometer designs using standard cells with regular layout

Formation of highly reliable Cu/low-k interconnects by using CVD Co barrier in dual damascene structures

Enhanced Grain Growth of Electroplated Copper on Cobalt-Containing Seed Layer

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