World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS

Abstract

World's first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9 th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor I on /I off ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.Introduction Downscaling of conventional CMOS device has reached its limitations and cost to develop sub 40 nm processes has dramatically increased. To overcome the CMOS shrinking limitation, various technologies such as high-k, metal gate, stress liner, and e-SiGe etc. are applied [1] or many new concept devices are reported [2][3][4].We propose a new concept for a novel 3D-FPGA using a-Si TFT configuration SRAM ( Fig. 1) over bulk CMOS logic to reduce FPGA die area, die cost and power [5]. 3D-FPGA is for prototype & low volume production. For high volume production, the TFT layer is replaced with metal layer (Fig. 2) during fabrication, which means FPGA die converts to timing-exact ASIC die without redesign effort, lowering die cost further and improving reliability. In this paper, we present the TFT fabrication technology & TFT device characteristics built over 9 layers of Cu interconnected CMOS circuits at processing temperature below 400C.Process technology Process flow for the TFT device on LSI is shown in Fig. 3. First, underlying LSI was fabricated on 300mm-Si Toshiba standard 90nm CMOS technology. After opening via's to connect the LSI to TFT, a-Si TFT' were fabricated below 400C, which is essential to maintain the reliability of Cu metal. This constraint limits the performance of TFT devices. Fig. 4 shows a cross sectional image of 9 metal layer CMOS with TFT layer (left Fig.) and a detailed TFT transistor (right Fig.). TFT transistor channel length is 180nm, with 20nm gate dielectric formed by plasma-TEOS. Fully silicided a-Si gate electrode (FUSI gate) is formed to control the Vth and boost the transistor performance. S/D is also fully silicided for higher current and to connect to underlying CMOS. NiPt and a-Si thickness is accurately controlled to form FUSI gate and S/D. TFT transistor image is shown in Fig. 5. TFT transistor performance is enhanced by using majority carrier accumulation devices. Table-1 shows the key features for this a-Si TFT technology demonstrating the densest integration for a-Si TFT in the industry. Key features of TFT processing used Toshiba 65nm CMOS fabrication techniques.Device characterization Fig. 6 (a) shows TFT transistor characteristi...

Monolithic 3-D FPGAs

“…In 2010, Naito et al [85] showed a monolithic 3-D FPGA in which the a-Si TFT-based SRAM configuration memory was stacked over the CMOS logic and routing circuits. The memory cell used nine transistors, unlike conventional bulk SRAM cells with six transistors; the three additional TFTs were used as a buffer to isolate the cell's storage node from the bitline for the read operation.…”

“…Cross-sectional SEM images of 3-D FPGA prototype chips: (a) nine-metal-layer CMOS logic circuits and a-Si TFT configuration memory[85];…”

Optimally Fortifying Logic Reliability through Criticality Ranking

“…This is because FPGA devices typically have regular and highly-scalable structures, as well as stringent demands on high performance and energy efficiency. For example, FPGAs that use a 22-nm high-k/metal gate process technology and operate with frequencies up to 1.5 GHz have been announced [7]. Unfortunately, CMOS technology scaling also poses several technical challenges to FPGA device's reliability.…”

Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

“…One promising way is 3D monolithic integration (3DMI), which can be broadly classified into two groups: a) active layer formation on a single wafer [1]- [6] and b) sequential stacking based on active layer transfer technology [7] [8]. Batude et al published their 3DIC researches based on molecular bonding technique with SOI wafer, Naito et al demonstrated 3D-FPGA with TFT SRAM, and low temperature poly-Ge CMOS technology was realized by Park et al As compared to TSV based 3D technology, the 3DMI technology can provide a low leakage current devices and a shortest wiring length for circuit design.…”