Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase Compensation

Yang, Bong-Jun; Qian, Huizhen Jenny; Shu, Yiyang; Zhou, Jie; Luo, Xun

doi:10.1109/cicc53496.2022.9772776

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…For high linearity, analog PAs, i.e., Class-A and Class-AB PAs, have been widely used with limited efficiency [4], [5], [6]. On the contrary, digital PAs have been widely investigated in recent years for their merits of high efficiency and flexibility of operation modes [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32]. The switching unit cells contribute to the high efficiency of digital PAs.…”

Section: Introductionmentioning

confidence: 99%

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

Tang

Qian

Yang

et al. 2023

IEEE J. Solid-State Circuits

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This article presents a digital polar Doherty switched-capacitor power amplifier (SCPA) using on-chip selfcalibration technique with storage capacitor array (SCA) to compensate the amplitude modulation (AM)-phase modulation (PM) distortion automatically for high data-rate signals. Such a self-calibration technique detects the AM-PM distortion at output and generates the related phase compensation in PM signals. The SCA is proposed to store control voltages of phase shifter for different amplitude code and decrease the settle time for high data-rate, which achieves fast locking of the calibration loop. Based on the proposed self-calibration with SCA, a polar Doherty SCPA is designed and fabricated in conventional 40-nm CMOS technology. This chip achieves 28.9-dBm peak output power (P sat ) and 43.9% peak drain efficiency (DE) at 1.8 GHz. It supports 100-MHz 64-QAM/10-MHz 1024-QAM signal with 22.6-/21.3-dBm average output power and 33.9%/32.1% average DE without digital pre-distortion (DPD).

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Section: Introductionmentioning

confidence: 99%

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

Tang

Qian

Yang

et al. 2023

IEEE J. Solid-State Circuits

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“…Examples include class-G PAs [16][17][18] with digital supply modulations, and Doherty PAs [19][20][21][22][23] and Outphasing PAs [24][25][26][27] with active load modulations. Other solutions include the Sub-Harmonic Switching (SHS) PA [28][29][30] and the Switched/Floated Capacitor Power Amplifier (SFCPA) [31], [32] with tri-state floating capacitors. Recent designs also demonstrate hybrid use of voltage-and current-mode PAs in digital Doherty PAs for balanced linearity and efficiency performance [33].…”

Section: Introductionmentioning

confidence: 99%

A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse

et al. 2022

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This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a Pout 1dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power (Pout) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is 1.24×/1.51×/1.72× at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent -27.1dB EVM, -31.31dBc ACLR, 14.6dBm average Pout and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves < -60 dBm LO leakage over the operating frequency range INDEX TERMS capacitor stacking, class-G DPA, CMOS, digital front-end, Doherty, linearity, N-path filter, polar modulation, power back off, transformer.

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Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase Compensation

Cited by 2 publications

References 7 publications

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse

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