VHDL-AMS behavioural modelling of a CMUT element

A CMUT read-out circuit with improved receive sensitivity using an adaptive biasing technique

“…Also, the graph shows uneven time steps to cover the data over the entire time span. The pull-in voltage is about 228 V, the same as the model in [4]. As it is shown in this figure, the CMUT sensitivity and conversion efficiency are increased as the DC bias level increases.…”

“…As it can be seen in this figure, the steady-state outputs are achieved after about 5μs and are equal to 9.38 V, 13.78 V and 18.22 V. As mentioned earlier, the switches' resistances and capacitor charge and discharge losses are the main non-idealities that cause deviations from the ideal multiplier factors in the DC-DC converter. To test the CMUT functionality for different DC bias levels, we have used a Verilog-AMS behavioral model (based on [4] and [11]). Fig.…”

“…Fig. 1 illustrates a typical graph of CMUT element efficiency versus its DC bias voltage [4]. As it is shown in this figure, the efficiency is generally low, but it significantly increases near the pull-in voltage.…”

“…By increasing the bias voltage, a point is reached where the electrostatic force overwhelms the restoring force. At this point, called the collapse or pull-in point, V B , the [4] membrane collapses down towards the substrate. It has been shown in [2]- [4] that the optimal DC bias voltage which provides maximum electro-mechanical conversion efficiency is close to this pull-in voltage.…”

“…In both cases, a DC bias larger than the AC voltage is applied to the device [2]. The sensitivity and efficiency of the device depends on the amount of this DC bias [3], [4].…”