Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

In this paper, we present a descriptive analysis of a performance index, V DIBLSS /(I on /I off), used for performance monitoring. Scaled n-and p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified V DIBL /(I on /I off) for monitoring the electrical characteristics of MOSFET devices is proposed due to the "quick measurements" required in the last step of the semiconductor manufacturing process. V DIBL /(I on /I off) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for V DIBL /(I on /I off) is much quicker than for V DIBLSS /(I on /I off), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as I on /I off and intrinsic gain, g m × r o , are reported using V DIBLSS /(I on /I off) and V DIBL /(I on /I off). V DIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since I on /I off is a sensitive function of threshold voltage, the estimates of the V DIBLSS /(I on /I off) and V DIBL /(I on /I off) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of V DIBLSS /(I on /I off) and V DIBL /(I on /I off) are hard to achieve. However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure. INDEX TERMS V DIBL /(I on /I off), V DIBLSS /(I on /I off), FinFETs, intrinsic gain, performance metrics, scaled MOSFETs.

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“…In this study, we also include some state-of-the-art scaled devices in [13] and [14] for comparison ( Fig. 6).…”

Section: Resultsmentioning

confidence: 99%

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Eng

Chang

et al. 2019

IEEE J. Electron Devices Soc.

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“…Highly doped Si 0.5 Ge 0.5 [12] (Si 0.98 C 0.02 ) epitaxies with boron (phosphorus) of 5 × 10 20 (1 × 10 20 ) cm −3 were formed as the S/D of the PFETs (NFETs), and silicon NS channels and substrate were undoped (1×10 15 cm −3 ). Punchthrough stopper (PTS) was doped with phosphorus (boron) of 2 × 10 18 cm −3 in the PFETs (NFETs).…”

Section: Device Design and Simulation Methodologymentioning

confidence: 99%

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

et al. 2020

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Excess source and drain (S/D) recess depth (T SD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (I off , I on) in three-stacked NS channels and parasitic bottom transistor (tr pbt), gate capacitance (C gg), intrinsic switching delay time (τ d), and static power dissipation (P static) are investigated quantitatively according to the T SD variations. More S/D dopants diffuse into the tr pbt with the deeper T SD , so the I off and I on increase due to raised current flowing through the tr pbt. Especially, the I off of PFETs remarkably increases above the certain T SD (T SD,critical) compared to NFETs. Furthermore, the I on contribution of each channels having the T SD,critical is the largest at the top NS channel and the tr pbt has the ignorable I on contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) I on contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The C gg also increases with the deeper T SD by increasing parasitic capacitance, but fortunately, the τ d decreases simultaneously due to the larger increasing rate of the I on than that of the C gg for all SoC applications. However, the P static enormously increases with the deeper T SD , and low power application is the most sensitive to the T SD variations among the SoC applications. Comprehensive analysis of the inevitable tr pbt effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

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“…As CMOS technology enters the 3 nm node, GAA nanosheet/nanowire becomes the most powerful competitor to replace FinFET technology because of its excellent control of SCEs [ 189 , 190 ]. As it was mentioned above, GAA devices mainly have two forms, horizontal [ 191 , 192 ] and vertical [ 46 , 193 , 194 ], and selective etching plays a very important role in these manufacturing processes. For the preparation of horizontal nanowires shown in Figure 32 , there are three main steps that require precise selective etching to prepare inner spacers and release dummy gates and nanowire channels.…”

Section: Advanced Etching For Nano-transistor Structuresmentioning

confidence: 99%

“…The thin thicknesses will increase the leakage and parasitic capacitance. The thicker thicknesses will increase the resistance between S/D when the device is turned on [ 191 , 192 ]. Inner spacers have greater challenges than conventional spacers where a higher etching selection ratio and etching accuracy are required [ 195 ].…”

Section: Advanced Etching For Nano-transistor Structuresmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

Cited by 88 publications

References 6 publications

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

State of the Art and Future Perspectives in Advanced CMOS Technology

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