Vertically integrated circuits at fermilab

Deptuch, G.; Demarteau, M.; Hoff, J.; Lipton, R.; Shenai, A.; Trimpl, M.; Yarema, R.; Zimmerman, T.

doi:10.1109/nssmic.2009.5402167

Cited by 10 publications

(18 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The presented results are the first to show that a three-dimensionally integrated readout for detection of X-rays could be built and its operation and parameters are at least the same as standard 2D counterparts. On the other hand the 3D technology supersedes older approaches by the density of electronics that can be put in a small footprint of a pixel, and by completely new approaches that can be applied in construction of detector systems [1] [6]. Obtaining definite analyses, including statistical parameters of the devices are still underway.…”

Section: Discussionmentioning

confidence: 99%

Results of tests of three-dimensionally integrated chips bonded to sensors

Deptuch¹

2013

2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)

View full text Add to dashboard Cite

Abstract-The VIPIC1 pixel readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments, typically using 8 keV Xrays at a synchrotron radiation facility. Technical hurdles related to a very aggressive alignment resulted in delays with delivery of 3D bonded wafers that eventually yielded operational devices. Recent improvements in alignment of wafers bonded with the Cu-Cu thermo-compression method and resorting to the Cu-DBI® bonding method started providing operational devices that were tested and led to the next steps. These were the tests with radioactive sources, emitting X-rays, executed after bonding of individual 3D dies to Silicon pixelated sensors for the first time. Results of these tests are presented.

show abstract

Section: Discussionmentioning

confidence: 99%

Results of tests of three-dimensionally integrated chips bonded to sensors

Deptuch¹

2013

2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)

View full text Add to dashboard Cite

show abstract

“…After nearly two decades of extensive development, 3-D integration technologies, materials, and facilities are almost ready for batch production. While numerous devices, such as DRAM and CPU using 3-D technologies, are still under development or custom test [4]- [8], a large variety of 3-D products, such as FPGA [9]- [11], CMOS image sensors [12]- [14], active pixel sensors [15]- [17], MEMS resonators [18]- [20], and accelerometers [21], have emerged in market.…”

Section: -D Integration Is Emerging As a Promising Technologymentioning

confidence: 99%

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Huang

Pan

Liu

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

View full text Add to dashboard Cite

Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between −65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.

show abstract

“…The readout within each group is zero-suppressed. The sparsification circuitry (similar to one used in the Mephisto chip [2]), allows a dead-time free readout. Each pixel contains a 5-bit long counter, which is designed for the operation at a high frame rate and therefore it should not overflow at the nominal operation of 10 µs per frame.…”

Section: Digitalmentioning

confidence: 99%

First Three-Dimensionally Integrated Chip for Photon Science

Maj¹,

Carini²,

Deptuch³

et al. 2013

Proceedings of the 21st International Workshop on Vertex Detectors — PoS(Vertex 2012)

View full text Add to dashboard Cite

We report on the results from testing of the first three-dimensionally integrated readout chip for pixel detectors, which application is in X-ray Photon Correlation Spectroscopy (XPCS) experiments on light sources. The chip was designed in the 130nm Tezzaron/GF process as a two-tier device with effectively 12 metal layers of routing. It counts about 1,700 transistors in total in 80x80um^2 pixels. The chip explores broadly the benefits of the 3D integration for pixel detectors, like full separation of analog and digital parts by placing them accordingly on distinct tiers, improved power distribution by using backside located pads and almost no periphery for achieving 4-side buttability. VIPIC1, as that is the name of the chip, was designed by FNAL in collaboration with AGH-UST. The tests are underway on the singulated devices from the first successfully bonded wafer pairs. Correct operation of all components tested so far was observed. This includes: full sparsified readout that is based on a priority encoder, pipelined inpixel hit acquisition with two alternately switched event counters, programming interfaces for permanent setting and disabling of a pixel and acquisition of hits from the analog part with full sensitivity to settings of discriminator thresholds. Current work is focused on measurements of pixel-to-pixel deterministic offsets, electronic noise and calibration of gain using injection of test charges. Every pixel features multiple connections across two-tier boundary. No faults were observed in the 3D bonding interface as well as the connectivity carried by through silicon vias was observed to be achieved on all dies that were qualified as good after wafer thinning. Despite of the long waiting for the first 3D chips, the test results are encouraging for the threedimensional integration technology as a cost and performance efficient alternative to the aggressive node down scaling.

show abstract

Vertically integrated circuits at fermilab

Cited by 10 publications

References 25 publications

Results of tests of three-dimensionally integrated chips bonded to sensors

Results of tests of three-dimensionally integrated chips bonded to sensors

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

First Three-Dimensionally Integrated Chip for Photon Science

Contact Info

Product

Resources

About