Validation of Turandot, a fast processor model for microarchitecture exploration

Moudgill, Mayan; Bose, Pradip; Moreno, Jaime H.

doi:10.1109/pccc.1999.749471

Cited by 38 publications

(38 citation statements)

References 9 publications

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“…An endeavor Turandot simulator [11,12] is further inventive effort which simulates a PowerPC architecture. Along with the aid of simultaneous multithread SMT the project was extended for multicore.…”

Section: Simulation Frameworkmentioning

confidence: 99%

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

Khari¹,

Kumar²,

Le³

et al. 2017

IJCNIS

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Abstract-A variety of technologies in recent years have been developed in designing on-chip networks with the multicore system. In this endeavor, network interfaces mainly differ in the way a network physically connects to a multicore system along with the data path. Semantic substances of communication for a multicore system are transmitted as data packets. Thus, whenever a communication is made from a network, it is first segmented into sub-packets and then into fixed-length bits for flow control digits. To measure required space, energy & latency overheads for the implementation of various interconnection topologies we will be using multi2sim simulator tool that will act as research bed to experiment various tradeoffs between performance and power, and between performance and area requires analysis for further possible optimizations.

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Section: Simulation Frameworkmentioning

confidence: 99%

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

Khari¹,

Kumar²,

Le³

et al. 2017

IJCNIS

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“…We utilize a generic, parameterized, out-of-order 8-way superscalar processor model called Turandot [16,17] with 32KB I and D-caches and a 2MB L2 cache. The overall pipeline structure (as reported in [16]), is repeated here in Figure 2. The modeled baseline microarchitecture is similar to a current generation microprocessor.…”

Section: Analytical Pipeline Modelmentioning

confidence: 99%

Optimizing pipelines for power and performance

Srinivasan¹,

Brooks²,

Gschwind³

et al.

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.

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“…A number of simulators for multiprocessors have been proposed in the literature [25,26,28,[43][44][45][46][47]. Among them, Simics [28], SimOS [46], SimpleScalar [43], and AMD SimNow [47] em ulate the processor at th e instruction set level.…”

Section: 3 1 S Ch Ed U Ler S Im U La To R Smentioning

confidence: 99%

“…SimpleScalar simulates a close derivative of MIPS architecture. Turandot [44] emulates PowerPC. A recent simulator called COTSon [45] uses AMD SimNow, and employs a statistical sampling technique th a t can selectively tu rn on and off the sim ulation to reduce the overall simulation time.…”

Section: 3 1 S Ch Ed U Ler S Im U La To R Smentioning

confidence: 99%

A flexible simulation framework for processor scheduling algorithms in multicore systems.

Manickam¹

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Validation of Turandot, a fast processor model for microarchitecture exploration

Cited by 38 publications

References 9 publications

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

Optimizing pipelines for power and performance

A flexible simulation framework for processor scheduling algorithms in multicore systems.

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