Using branching time temporal logic to synthesize synchronization skeletons

Emerson, E. Allen; Clarke, Edmund M.

doi:10.1016/0167-6423(83)90017-5

Cited by 530 publications

(326 citation statements)

References 7 publications

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“…Existing synthesis methods in the literature mostly focus on deriving the synchronization skeleton of a program from its specification (expressed in terms of temporal logic expressions or finite-state automata) [Emerson and Clarke 1982;Manna and Wolper 1984;Pnueli and Rosner 1989a;1989b;Attie …”

Section: Revising Real-time Unity Programs: Hardness Resultsmentioning

confidence: 99%

Revising UNITY Programs: Possibilities and Limitations

Ebnenasir

Kulkarni

Bonakdarpour

2006

Lecture Notes in Computer Science

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We concentrate on automatic addition of untimed and real-time UNITY properties to programs by local redesign. The main focus of this paper is to identify instances where addition of UNITY properties can be achieved efficiently (in polynomial time) and where the problem of adding UNITY properties is difficult (NP-complete).Regarding addition of UNITY properties in polynomial time, we present a sound and complete algorithm that adds a single leads-to property (respectively, bounded-time leads-to property) and a conjunction of unless, stable, and invariant properties (respectively, bounded-time unless and stable) to an existing untimed (respectively, real-time) UNITY program. Since ensures can be expressed as a conjunction of a leads-to and unless, our algorithms can also be used to add one ensures property along with a conjunction of safety properties.Regarding hardness results, we show that (1) while one leads-to (respectively, ensures) property can be added in polynomial time, the problem of adding two such properties (or any combination of leads-to and ensures) is NP-complete, (2) if maximum non-determinism is desired then the problem of adding even a single leads-to property is NP-complete, and (3) the problem of providing maximum non-determinism while adding a single bounded-time leads-to property to a real-time program is NP-complete (in the size of the time-abstract bisimulation representation of the program) even if the original program satisfies the corresponding unbounded leads-to property.

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Section: Revising Real-time Unity Programs: Hardness Resultsmentioning

confidence: 99%

Revising UNITY Programs: Possibilities and Limitations

Ebnenasir

Kulkarni

Bonakdarpour

2006

Lecture Notes in Computer Science

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“…This bug actually is difficult to be found using simulation because one has to simulate that all the cells with VPI_VCI not equaling to 000000 cannot be matched. With formal verification, one can easily detect this bug using property Ingress_P 6 . According to this property, every state in the state space should be (VPI_VCI_IN != 000000) AND (MATCH_FOUND = 0), provided that the incoming VPI_VCI_IN does not equal to 000000.…”

Section: Table 2 Verification Results Of Sample Properties In Formalcmentioning

confidence: 99%

“…In [6], E. M. Clarke et al proposed the method of constructing concurrent programs from CTL formulas. The result program covers one, but not all, behavior of the formulas.…”

Section: Compositional Verification and Environment Synthesismentioning

confidence: 99%

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Compositional Verification of a Switch Fabric from Nortel Networks

Peng

Tahar

Mokhtari

2003

Formal Methods and Software Engineering

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With the development of ASIC designs, simulation cannot cover all the corner cases in a complicated design. Model checking is a fully automatic approach to verify a finite state machine against its temporal specifications. However, its application is limited by the size of the system to be verified. Compositional verification and model reduction are two possible methods to tackle this problem. In this paper, we propose a verification framework based on assumeguarantee compositional model checking, where we can apply model checking to do exhaustive verification at the module level and conduct global properties via compositional reasoning. In this framework, temporal specifications are synthesized into Verilog modules. In case a module under verification is beyond the capability of model checking, the proposed model reduction algorithm is used. We implemented the framework on top of the VIS tool and applied it on an ATM switch fabric from Nortel Networks.

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“…Different from model checking [3,4], bounded model checking focuses on catching design flaws within a bounded number of steps, and therefore does not guarantee the design to be free from errors. Naturally, one wonders whether bounded model checking can be extended to be complete.…”

Section: Introductionmentioning

confidence: 99%

Proving ∀μ-Calculus Properties with SAT-Based Model Checking

Wang

2005

Formal Techniques for Networked and Distributed Systems - FORTE 2005

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Abstract. In this paper, we present a complete bounded model checking algorithm for the universal fragment of µ-calculus. The new algorithm checks the completeness of bounded proof of each property on the fly and does not depend on prior knowledge of the completeness thresholds. The key is to combine both local and bounded model checking techniques and use SAT solvers to perform local model checking on finite Kripke structures. Our proof-theoretic approach works for any property in the specification logic and is more general than previous work on specific properties. We report experimental results to compare our algorithm with the conventional BDD-based algorithm.

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Using branching time temporal logic to synthesize synchronization skeletons

Cited by 530 publications

References 7 publications

Revising UNITY Programs: Possibilities and Limitations

Revising UNITY Programs: Possibilities and Limitations

Compositional Verification of a Switch Fabric from Nortel Networks

Proving ∀μ-Calculus Properties with SAT-Based Model Checking

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