Using a Complementary Emulation-Simulation Co-Design Approach to Assess Application Readiness for Processing-in-Memory Systems

Abstract

Disruptive changes to computer architecture are paving the way toward extreme scale computing. The co-design strategy of collaborative research and development among computer architects, system software designers, and application teams can help to ensure that applications not only cope but thrive with these changes. In this paper, we present a novel combined co-design approach of emulation and simulation in the context of investigating future Processing in Memory (PIM) architectures. PIM enables co-location of data and computation to decrease data movement, to provide increases in memory speed and capacity compared to existing technologies and, perhaps most importantly for extreme scale, to improve energy efficiency. Our evaluation of PIM focuses on three mini-applications representing important production applications. The emulation and simulation studies examine the effects of locality-aware versus locality-oblivious data distribution and computation, and they compare PIM to conventional architectures. Both studies contribute in their own way to the overall understanding of the application-architecture interactions, and our results suggest that PIM technology shows great potential for efficient computation without negatively impacting productivity.2014 Hardware-Software Co-Design for High Performance Computing 978-1-4799-7564-8/14 $31.00

Traffic Congestion Control based In-Memory Analytics: Challenges and Advantages

“…Because of the difficulties faced in attempting to use all these data, there is a need to centralize access to image and video traffic data stored at the data centers of different divisions as well as centralizing access to traffic management facilities, equipment and application systems. As in [14], GPS data are available and accessible and provide information about roads and destinations. At a minimum, this can show where traffic is heading, allowing predictions to be made about where traffic problems will occur, and to create a simulation which can be used for transport system planning and optimization.…”

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube

“…In [15], PIM is comprised of CPUs and GPUs. Reference [16] augment the logic die with a cluster of 16 lightweight general purpose cores with two levels of caches. Tesseract [17] features a network of memory cubes, each accommodating a cluster of in-order cores with L1 caches.…”