Two Low-Complexity Reliability-Based Message-Passing Algorithms for Decoding Non-Binary LDPC Codes

Chen, Chao-Yu; Huang, Qin; Chao, Chi-chao; Lin, Shu

doi:10.1109/tcomm.2010.091310.090327

Cited by 86 publications

(54 citation statements)

References 28 publications

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“…The algorithm proposed in [17] provides good results for low-rate codes, however, for high-rate codes, such as (837, 723) code, it has an early error floor which makes it impractical for the applications that require such codes. Furthermore, the early error floor also appears in the algorithm in [3]. In fact, this algorithm is the same as the one in [17] with a different initialization, as is confirmed in [10].…”

Section: Fixed-point Analysissupporting

confidence: 58%

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

García-Herrero

Canet

Valls

2012

Circuits Syst Signal Process

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A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modified to avoid computing and storing a matrix of dimension N × 2 q , for a code (N, K) over GF(2 q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837, 723) non-binary code over GF(2 5 ), requiring 590220 xor gates and achieving a throughput of 89 Mbps. Additionally, it was implemented in a Virtex-VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps.

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Section: Fixed-point Analysissupporting

confidence: 58%

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

García-Herrero

Canet

Valls

2012

Circuits Syst Signal Process

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“…In a parallel thread, works such as [10] and [49], among others, have explored various aspects of decoding of non-binary LDPC codes. Codes with efficient encoding and decoding were proposed in [52].…”

Section: Introductionmentioning

confidence: 99%

Non-Binary Protograph-Based LDPC Codes: Enumerators, Analysis, and Designs

Dolecek

Divsalar

Sun

et al. 2014

IEEE Trans. Inform. Theory

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Abstract-This paper provides a comprehensive analysis of non-binary low-density parity check (LDPC) codes built out of protographs. We consider both random and constrained edgeweight labeling, and refer to the former as the unconstrained non-binary protograph-based LDPC codes (U-NBPB codes) and the latter as the constrained non-binary protograph-based LDPC codes (C-NBPB codes). Equipped with combinatorial definitions extended to the non-binary domain, ensemble enumerators of codewords, trapping sets, stopping sets, and pseudocodewords are calculated. The exact enumerators are presented in the finite-length regime, and the corresponding growth rates are calculated in the asymptotic regime. We then present an EXIT chat tool for computing the iterative decoding thresholds of protograph-based LDPC codes followed by several examples of finite-length U-NBPB and C-NBPB codes with high performance. Throughout the paper, we provide accompanying examples which demonstrate the advantage of non-binary protograph-based LDPC codes over their binary counterparts and over random constructions. The results presented in this paper advance the analytical toolbox of non-binary graph-based codes.

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“…IHRB algorithm brings off a substantial coding gain with less overhead. Chen et al [19], demonstrated the iterative soft-reliability-based (ISRB algorithm for non-binary LDPC codes. This architecture results in good error performance and fast convergence.…”

Section: Related Workmentioning

confidence: 99%

Efficient high throughput decoding architecture for non-binary LDPC codes

Murugan¹,

Banuselvasaraswathy²,

Gayathree³

et al. 2018

IJET

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This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

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Two Low-Complexity Reliability-Based Message-Passing Algorithms for Decoding Non-Binary LDPC Codes

Cited by 86 publications

References 28 publications

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

Non-Binary Protograph-Based LDPC Codes: Enumerators, Analysis, and Designs

Efficient high throughput decoding architecture for non-binary LDPC codes

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