Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor

Singh, Shailendra; Raj, Balwinder

doi:10.1007/s10825-020-01496-4

Cited by 42 publications

(4 citation statements)

References 28 publications

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“…For better carrier transport simulation, we used the recombination model with dopingdependent mobility. However, the electrons' tunneling is estimated via the non-local band model to band tunneling [30,31]. This model will consider the point-to-point tunneling at the energy band gradient.…”

Section: Device Structure and Simulation Frameworkmentioning

confidence: 99%

Design and Investigation of Gate Stacked Vertical TFET with N+ SiGe Pocket Doped Heterojunction for Performance Enhancement

Gupta¹,

Wariya²,

Singh³

2021

Preprint

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In this paper, a novel delta-doped N + Silicon-Germanium Gate Stacked Triple Metal Gate Vertical TFET (Delta doped N + GS TMG VTFET) is proposed and investigated using the Silvaco TCAD simulation tool. Four different combinations were presented and compared with and without the gate stacking method and Si0.2Ge0.8 N + pocket delta-doped layer to render the optimized results. Among all, Delta doped N + GS TMG VTFET structure comes out with a very steep sub-threshold slope (9.75 mV/dec), 40 % lower than the first configuration of TMG VTFET. The inclusion of the N + delta-doped layer between the source and channel and gate will enhance the ON-state drive current performance by reducing the OFF-state leakage current. This happens due to the lower bandgap of the N + delta-doped layer cause narrow BTBT, which results in a high drive current. The Triple metal gate is designed to mitigate the ambipolar conduction by modulating the optimized wok function at 4.15, 4.3, and 4.15 eV. The distribution of the source channel in the vertical structure will enhance the device's scalability due to the electron tunneling moves in the vertical electric field direction. The optimally constructed structure demonstrates improved performance, such as a high ION/IOFF current ratio (~ 1013) and sub-threshold voltage (0.33 V). The results obtained from the proposed device make it suitable for the ultra-low-power device application.

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Section: Device Structure and Simulation Frameworkmentioning

confidence: 99%

Design and Investigation of Gate Stacked Vertical TFET with N+ SiGe Pocket Doped Heterojunction for Performance Enhancement

Gupta¹,

Wariya²,

Singh³

2021

Preprint

Self Cite

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“…The early stages of TFET-based biosensor designs used physical doping, which complicates the manufacturing process and raises the overall thermal budgeting for high-temperature thermal annealing [10,11]. A TFET is a p-i-n structured device that works on the Band to band tunnelling principle.…”

Section: Introductionmentioning

confidence: 99%

Simulation and Performance Evaluation of Charge Plasma Based Dual Pocket Biosensor using SiGe-Heterojunction TFET Design

Paul

2022

Silicon

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Conventional biosensor designs are often vulnerable to issues like random dopant fluctuations (RDFs) and high thermal budgets due to their design and the device they are based on. The main reason behind such issues is the complexity of maintaining uniform doping levels throughout the device structure. This manuscript investigates a biosensor structure utilizing a dual pocket junctionless SiGe-Heterostructured TFET design to overcome such shortcomings. The implementation of the doping charge plasma technique with the uniform doping of along an integrated SiGe-Heterostructure layer has improved the tunneling process while also effectively eliminating issues like random dopant fluctuations (RDF). Again the overall performance also depends on the sensitivity of the sensor design. Increasing the trapping area for biomolecules at the same technological node by increasing the pocket length or by adding a pocket region leads to rapid changes in the sensor’s electric properties owing to shifting dielectric constants (k) and charge densities (in both positive and negative situations), improving in the overall detection process. The influence of these parameters on the device’s Drain current, Surface Potential, Electron Tunneling Rate (ETR), Subthreshold Swing (SS), and I on /I off ratio is also explored. The introduction of the added pocket region gives us scalability while also showing a higher sensitivity of for a dielectric constant being 12 and neutrally charged while rising to nearly if the molecules are positively charged. With the improvement in drain current sensitivity due to the additional pocket and junctionless design, this work will undoubtedly give researchers a roadmap for the future generation of highly sensitive biosensor alternatives.

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“…A straight forward approach is required to reduce the energy consumption at the rapid scaling of supply voltage and to maintain the transistor output because of decrease in dynamic power. This fundamental boundary to the scaling of threshold voltage rises from MOSFETs subthreshold slope at room temperature 60 mV/decade [4]. Recently, the reduction of leakage using steep transistors for subthreshold has gained considerable attention [5].…”

Section: Introductionmentioning

confidence: 99%

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Singh

Raj

2020

Silicon

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In this paper, a new technique ONOFIC is proposed and implemented for designing the SiGe heterojunction 2D double gate Vertical t-shaped TFET as an inverter circuit for low power applications. Initially, simulation done for both P-type and N-type of Vertical tTFET with same attributes using Sentaurus TCAD simulation tool. Thereafter, mixed mode technique is employed to understand the inverter circuit simulation's electrical characteristics and circuit efficiency. The workfucntion used for n-type Vertical TFET is 4.5 eV and for p-type Vertical TFET is 5.6 eV respectively. A 2D analytical model also implemented to capture the affecting parameters of leakage current and depletion length of the proposed model. Moreover, a new block technique named ONOFIC is inserted between the pull-up network and pull-down network of the circuit to regulator the trade-off between the power dissipation and reduced device dimensions. The method offers an excellent agreement between the propagation delay and power dissipation for designing efficient logic circuit. This article compares the efficiency of logic circuit like NAND, NOR and inverter circuit by estimating the power-delay product (PDP) with the conventional logic designs. The performance result show that the proposed model significantly reduces the leakage current for low power circuit applications.

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Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor

Cited by 42 publications

References 28 publications

Design and Investigation of Gate Stacked Vertical TFET with N+ SiGe Pocket Doped Heterojunction for Performance Enhancement

Design and Investigation of Gate Stacked Vertical TFET with N+ SiGe Pocket Doped Heterojunction for Performance Enhancement

Simulation and Performance Evaluation of Charge Plasma Based Dual Pocket Biosensor using SiGe-Heterojunction TFET Design

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

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