Tunable n-Type Doping of Carbon Nanotubes through Engineered Atomic Layer Deposition HfO_X Films

Abstract

Although digital systems fabricated from carbon-nanotube-based field-effect transistors (CNFETs) promise significant energy efficiency benefits, realizing these benefits requires a complementary CNFET technology, i.e., CNFET CMOS, comprising both PMOS and NMOS CNFETs. Furthermore, this CNFET CMOS process must be robust (e.g., airstable), tunable (e.g., ability to control CNFET threshold voltages), and silicon CMOS compatible (to integrate within existing manufacturing facilities and process flows). Despite many efforts, such a silicon CMOS compatible CNT doping strategy for forming NMOS CNFETs does not exist. Techniques today are either not air-stable (using reactive low work function metals), not solid-state or silicon CMOS compatible (employing soluble molecular dopants in ionic solutions), or have not demonstrated precise control over the amount of doping (for setting threshold voltage, V T ). Here, we demonstrate an electrostatic doping technique that meets all of these requirements. The key to our technique is leveraging atomic layer deposition (ALD) to encapsulate CNTs with nonstoichiometric oxides. We show that ALD allows for precise control of oxide stoichiometry, which translates to direct control of the amount of CNT doping. We experimentally demonstrate the ability to modulate the strength of the p-type conduction branch by >2500× (measured as the change in current at fixed bias), realize NMOS CNFETs with n-type conduction ∼500× stronger than p-type conduction (also measured by the relative current at fixed biases), and tune V T over a ∼1.5 V range. Moreover, our technique is compatible with other doping schemes; as an illustration, we combine electrostatic doping and low work function contact engineering to achieve CNFET CMOS with symmetric NMOS and PMOS (i.e., CNFET ON-current for NMOS and PMOS is within 6% of each other). Thus, this work realizes a solid-state, air-table, very large scale integration and silicon CMOS compatible doping strategy, enabling integration of CNFET CMOS within standard fabrication processes today.

Seebeck-voltage-triggered self-biased photoelectrochemical water splitting using HfOx/SiOx bi-layer protected Si photocathodes

“…H-terminated and SiO x -grown p-Si (100) wafers were prepared through the treatment of diluted hydrofluoric acid and hot-water-oxidation, respectively, and these wafers were deposited with an amorphous HfO x thin film using the atomic layer deposition (ALD) process 39–41 . The chemical composition of HfO x was confirmed using energy-dispersive X-ray spectroscope (EDXS) mapping and X-ray photoelectron spectroscopy (XPS) spectra (See Supplementary Figs 1 and 2).…”

Chirality‐Enriched Carbon Nanotubes for Next‐Generation Computing

“…This dual doping strategy has allowed the realization of highly symmetric n-type and p-type CMOS TFTs, with the resulting CMOS logic gates (i.e., NOT, NAND, and NOR) possessing high uniformity and performance metrics. [102] Given that post-processing purification techniques have achieved the highest s-SWCNT enrichment purities, significant efforts have been made toward the selective placement of solution-processed SWCNTs on target substrates. Early efforts in selective placement demonstrated s-SWCNT channels of percolating random networks and aligned films, while more recent efforts have focused on selective SWCNT placement with controllable pitch.…”

“…This oxide doping scheme has also been confirmed to be compatible with work function metal doping strategies, allowing a dual doping strategy for SWCNT CMOS TFTs. This dual doping strategy has allowed the realization of highly symmetric n‐type and p‐type CMOS TFTs, with the resulting CMOS logic gates (i.e., NOT, NAND, and NOR) possessing high uniformity and performance metrics 102…”

Nanosystems, Edge Computing, and the Next Generation Computing Systems

“…The evolution of computer technologies, enabling increased computing power and improved SWaP, has taken the switching speed or clock frequency of the processors from 750 kHz (Intel 4004) to 8.6 GHz (AMD’s FX) [154]. As the processor merits (e.g., the loosely adopted trend of doubling of transistor number on a chip per two years, i.e., Moore’s law) is approaching its current limits, novel processor architectures based on CNTs [149,195,196,197,198,199], or other nanomaterials [146,177] are being explored with tremendous prospects for the next generation computation and communication systems.…”

“…CNTs are large aspect-ratio quantum wires [196,216,246,247] with promising electronic, plasmonic [145], thermal, and mechanical properties [188,248], and can be arranged and integrated compactly [47,198,200,249,250,251,252] towards new computer systems [217,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267]. CNTs, as single carbon-atom thick cylindrical current carriers, have micrometers long electronic coherence lengths with electron mobility ~70 times higher than silicon and ~25% higher than other semiconductor materials.…”