TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

Abstract

Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as intermediate carrier and wiring device for IC components like logics, memories and sensors. Due to custom specific front and back side wiring interposers enable to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. High density copper filled TSVs with high aspect ratio as well as high density multi layer wiring using electro plated copper as conductive material and low loss dielectrics enable high performance signal transmission at interposer level without serious losses by parasitic effects. This paper presents the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer level assembly with IC components. Special focus is drawn on the TSV formation process including via etching, isolation and filling as well as front side high density wiring and subsequent backside processing of the thin TSV wafers. In this context, also temporary wafer to wafer bonding which is required for backside processing of thin TSV wafers is discussed. The final interposers which carry one or more IC components have lateral dimensions up to several square centimeters and thicknesses between 50-100 m. They include up to several thousands of TSVs per device with a single electrical resistance between 4.9-5.7 mOhms. All processes were run using production equipment at 200 mm wafers

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors

“…3) Hybrid Paradigm Using 2.5D On-chip Voltage Regulators with Interposer: Fig.4(c) gives a cross-section view of a hybrid power delivery system paradigm utilizing a 2.5D stacking silicon interposer, which is commonly used to extend the communication bandwidth of many-core processors [34]. The on-chip voltage regulators and the target processor chip are both mounted on the silicon interposer with micro-bumps.…”

Process modeling of dry etching for the 3D-integration with tapered TSVs

“…The most widely so called Bosch Process is used to fabricate vias with vertical sidewalls [1]. For Applications like interposers for processors, there exists the demand to produce TSVs with high aspect ratios [2] due to the high connection density and the necessary minimal thickness of the module caused by the assembly process. Subsequent processing of these etched holes in form of liner, barrier and seed layer deposition can become challenging and therefore increases costs.…”

Thermo-mechanical design and optimization of micro copper pillar bump for electrical interconnection in 2.5D IC integration

“…Zoschke et al reported their whole process for wafer level fabrication of 2.5D SiP modules , where the silicon interposer in the flip clip was bonded to a pin grid array (PGA) organic substrate [7]. While for the whole 2.5D IC integration process using ball grid array (BGA) organic substrate , the Cu/low-k silicon interconnected with silicon interposer through I lCPBs will undergo three times of lead free reflow process : a. the first level assembly between Cu/low-k silicon die and silicon interposer wafer , b. the second level component assembly between the silicon interposer and organic substrate , c. the third level assembly between the component and printed circuit board (PCB).…”