Transistor roadmap projection using predictive full-band atomistic modeling

Salmani-Jelodar, Mehdi; Kim, S.; Ng, Kwok K.; Klimeck, Gerhard

doi:10.1063/1.4894217

Cited by 14 publications

(16 citation statements)

References 19 publications

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“…In other words, it has to start from the end of Moore's law, to which current technology is rapidly approaching. The critical size limit is predicted to be 5 nm; at this space scale quantum effects such as tunneling and carrier confinement affect device performance [7]. In this view, the effects due to the device's shape and size gain essential importance, thereby making their study in systems with edges such as ribbons and quantum dots a paramount priority.…”

Section: Introductionmentioning

confidence: 99%

Electro-optical properties of phosphorene quantum dots

et al. 2017

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We study electronic and optical properties of single layer phosphorene quantum dots with various shapes, sizes, and edge types (including disordered edges) subjected to an external electric field normal to the structure plane. Compared to graphene quantum dots, in phosphorene clusters of similar shape and size there is a set of edge states with energies dispersed at around the Fermi level. These states make the majority of phosphorene quantum dots metallic and enrich the phosphorene absorption gap with low-energy absorption peaks tunable by the electric field. The presence of the edge states dispersed at around the Fermi level is a characteristic feature that is independent of the edge morphology and roughness.

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Section: Introductionmentioning

confidence: 99%

Electro-optical properties of phosphorene quantum dots

et al. 2017

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“…Then, SS for gate stack with different SiO 2 interface layer is estimated using equations 5 and 6. As T SiO2 increases and T OX decreases, the gate tunneling begins to deteriorate the performance and saturates SS, which shows there are other factors such as gate leakage, and source to drain tunneling [3] in determination of SS and equation 6 will not work well at that point.…”

Section: Methodsmentioning

confidence: 99%

“…Gate leakage results from the tunneling of electrons through the potential barrier between the gate and the channel. I Gate is exponentially related to the oxide thickness (T OX = T SiO2 +T high−k ) and oxide effective mass [3,16]. (Fig.…”

Section: Methodsmentioning

confidence: 99%

“…It is known that not only EOT, but also the physical oxide thickness plays important roles in SCEs. However, it is not clear what the solution is as the gate lengths of MOSFETs approach below 20 nm [1, 3,10].…”

mentioning

confidence: 99%

“…To mitigate the gate tunneling current in a thin oxide layer of ultra-scaled MOSFETs, high-k dielectrics are used [2,3]. However, due to the thicker high-k gate oxides, performance drops have been observed in the ultra-scaled MOSFETs with k > 30 [4][5][6][7][8][9].…”

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confidence: 99%

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Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

Salmani-Jelodar

Ilatikhameneh

Kim

et al. 2016

IEEE Trans. Nanotechnology

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A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as SiO2, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness (TOX) for each gate stack, including SiO2 interface layer and one high-k material. For the same EOT, Al2O3 (k=9) over 3Å SiO2 provides the best performance, while for HfO2 (k=20) and La2O3 (k=30), SiO2 thicknesses should be 5Å and 7Å, respectively. The effects of using high-k oxides and gate stacks on the performance of ultra-scaled MOSFETs are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.

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