2014 IEEE Conference and Expo Transportation Electrification Asia-Pacific (ITEC Asia-Pacific) 2014
DOI: 10.1109/itec-ap.2014.6941230
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Cited by 10 publications
(4 citation statements)
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“…The reason behind improved current sharing is; at a lower gate resistance, the switching speed increases and the effect of V th mismatch become less significant. Another way is to add a suitable resistance only to the gate of the fast device with the lower V th (Du et al, 2014). The fundamental principle behind adding the resistance is to delay the driving signal of the fast device (Du et al, 2014).…”
Section: Imbalance Mitigation Via Source or Gate Resistorsmentioning
confidence: 99%
See 1 more Smart Citation
“…The reason behind improved current sharing is; at a lower gate resistance, the switching speed increases and the effect of V th mismatch become less significant. Another way is to add a suitable resistance only to the gate of the fast device with the lower V th (Du et al, 2014). The fundamental principle behind adding the resistance is to delay the driving signal of the fast device (Du et al, 2014).…”
Section: Imbalance Mitigation Via Source or Gate Resistorsmentioning
confidence: 99%
“…Another way is to add a suitable resistance only to the gate of the fast device with the lower V th (Du et al, 2014). The fundamental principle behind adding the resistance is to delay the driving signal of the fast device (Du et al, 2014). Symmetrical layout is requisite for achieving promising results for both methods.…”
Section: Imbalance Mitigation Via Source or Gate Resistorsmentioning
confidence: 99%
“…Another reason is the asymmetry of the PCB layout, which has a negative effect on the current sharing of the devices [13]. Moreover, different temperature rise and electromagnetic interference (EMI) between parallel devices are caused by both types of unbalances, reducing the reliability of devices and system [14].…”
Section: Introductionmentioning
confidence: 99%
“…In this way, the impedances of the gate loops are differentiated, suppressing the dynamic unbalance only during turn-on transient. In [14], an extra resistor to the gate of the parallel-connected SiC MOSFET with the lowest threshold is added. As a result, the charging process of C iss of this particular SiC MOSFET is delayed, suppressing the turn-on dynamic unbalance.…”
Section: Introductionmentioning
confidence: 99%