Towards improved survivability in safety-critical systems

Abella, Jaume; Cazorla, Francisco J.; Quiñones, Eduardo; Grasset, Arnaud; Yehia, Sami; Bonnot, Philippe; Gizopoulos, Dimitris; Mariani, Riccardo; Bernat, Guillem

doi:10.1109/iolts.2011.5994536

Cited by 17 publications

(14 citation statements)

References 15 publications

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“…The exact analytical expressions of reliability and safety have been derived and evaluated on the interval [0, 200000] (flight hours), which is a typical lifetime of avionics systems [19,20]. Failure rates and coverage probabilities that have been used are given in Table 1.…”

Section: Numerical Resultsmentioning

confidence: 99%

Fault tolerant smart transducer interfaces for safety-critical avionics applications

Bouanen¹,

Thibeault²,

Savaria³

et al. 2013

2013 IEEE/AIAA 32nd Digital Avionics Systems Conference (DASC)

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Section: Numerical Resultsmentioning

confidence: 99%

Fault tolerant smart transducer interfaces for safety-critical avionics applications

Bouanen¹,

Thibeault²,

Savaria³

et al. 2013

2013 IEEE/AIAA 32nd Digital Avionics Systems Conference (DASC)

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“…We consider platforms with m = [2,16] processors. On each processor, there can be up to 10 tasks, where n = [1,10].…”

Section: A System Settingmentioning

confidence: 99%

“…The transition from uniprocessors to multiprocessors has been taking place over the last few years to meet the increasing demand for computation power [2]. However, moving to multiprocessor platforms breaks most of the well-known locking protocols and schedulability analysis approaches that are used on uniprocessor platforms, which can only manage resources that are accessed from one processor (local resources).…”

Section: Introductionmentioning

confidence: 99%

New schedulability analysis for MrsP

Zhao

Garrido

Burns

et al. 2017

2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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Abstract-In this paper we consider a spin-based multiprocessor locking protocol, named the Multiprocessor resource sharing Protocol (MrsP). MrsP adopts a helping-mechanism where the preempted resource holder can migrate. The original schedulability analysis of MrsP carries considerable pessimism as it has been developed assuming limited knowledge of the resource usage for each remote task. In this paper new MrsP schedulability analysis is developed that takes into account such knowledge to provide a less pessimistic analysis than that of the original analysis. Our experiments show that, theoretically, the new analysis offers better (at least identical) schedulability than the FIFO non-preemptive protocol, and can outperform FIFO preemptive spin locks under systems with either intensive resource contention or long critical sections.The paper also develops analysis to include the overhead of MrsP's helping mechanism. Although MrsP's helping mechanism theoretically increases schedulability, our evaluation shows that this increase may be negated when the overheads of migrations are taken into account. To mitigate this, we have modified the MrsP protocol to introduce a short non-preemptive section following migration. Our experiments demonstrate that with migration cost, MrsP may not be favourable for short critical sections but provides a better schedulability than other FIFO spin-based protocols when long critical sections are applied.

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“…Those semiconductor technologies needed for performance reasons, however, lead to an increased number of transient faults due to higher susceptibility to cosmic rays and alpha particles, as well as due to intermittent faults caused by small defects that grow enough due to degradation to produce faults under some particular environmental conditions (e.g., low voltage, high temperature) [3]. Permanent faults also arise either because defects grow enough until they cause permanent faults, or simply because they escaped post-silicon test [3].…”

Section: Introductionmentioning

confidence: 99%

“…Permanent faults also arise either because defects grow enough until they cause permanent faults, or simply because they escaped post-silicon test [3]. Transient and permanent faults lead to errors that can be tolerated to some extent in some markets, but cannot in CRTES where stringent correctness constraints call for means to prevent faults from jeopardising the safety of those systems.…”

Section: Introductionmentioning

confidence: 99%

Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems

Hernández

Abella

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Safety-relevant systems in the automotive domain often implement features such as lockstep execution for error detection, and reset and reexecution for error correction. Lightlockstep has already been adopted in some such systems due to its relatively low implementation cost given that it does not require deep changes into non-lockstep hardware. Instead, as only off-core activities (i.e. data/addresses sent) need to be compared across different cores, light-lockstep designs are lowly intrusive. This approach has been proven sufficient to guarantee functional correctness of the system in the presence of errors in the cores, in particular in relation with certification against safety standards such as ISO26262 in the automotive domain. However, error detection in light-lockstep systems may occur long after the error actually occurs, thus jeopardising timing guarantees, which are as critical as functional ones in hard real-time systems.In this paper we analyse the timing behaviour of errors due to transient and permanent faults in light-lockstep systems. Our results show that the time elapsed until an error is detected can be inordenately large, especially for permanent faults. Based on this observation and building upon the specific characteristics of light-lockstep systems, we propose LiVe (Lightly Verbose), a new mechanism to enforce the early detection of errors, due to both transient and permanent faults, thus enabling the computation of tight error detection timing bounds. We also analyse how existing mechanisms for error recovery in multicore systems increase their effectiveness when light-lockstep operates in LiVe mode in the context of mixed-criticality workloads.

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Towards improved survivability in safety-critical systems

Cited by 17 publications

References 15 publications

Fault tolerant smart transducer interfaces for safety-critical avionics applications

Fault tolerant smart transducer interfaces for safety-critical avionics applications

New schedulability analysis for MrsP

Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems

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