Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation

Iturbe, Xabier; Keymeulen, Didier; Yiu, Patrick; Berisford, Dan; Hand, K. P.; Carlson, R. W.; Özer, Emre

doi:10.1109/ahs.2015.7231151

Cited by 12 publications

(4 citation statements)

References 14 publications

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“…A microprocessor can be used alone to perform the image processing and star identification algorithms in software, but better results in terms of performance can be achieved if the microprocessor is combined with an FPGA and the image processing operations are implemented in hardware [27]. The FPGA can speed up those operations that are parallelizable such as the image acquisition or the noise filtering procedures mentioned before, while the microprocessor performs complex tasks such as the centroid calculation or the star identification algorithms [28]. As explained in the Introduction, SRAM-based FPGAs are commonly used as onboard data processing devices in satellites due to their high densities, processing speed, and low cost.…”

Section: Radiation-induced Errors In Star Trackersmentioning

confidence: 99%

Toward a Fault-Tolerant Star Tracker for Small Satellite Applications

Aranda

Reviriego

Maestro

2020

IEEE Trans. Aerosp. Electron. Syst.

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Star trackers are autonomous, high-accuracy electronic systems used to determine the attitude of a spacecraft. In recent years, Commercial Off-The-Shelf (COTS)-based star trackers are growing in importance for low-cost and shortduration missions, but their fault tolerance against soft errors has not been studied in detail. In this paper, we propose a selfhealing system protected with ad-hoc techniques that can be used as the first step to implement a fault tolerant COTS-based star tracker for smallsat applications.

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Section: Radiation-induced Errors In Star Trackersmentioning

confidence: 99%

Toward a Fault-Tolerant Star Tracker for Small Satellite Applications

Aranda

Reviriego

Maestro

2020

IEEE Trans. Aerosp. Electron. Syst.

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“…The use of a microcontroller allows for unique identification and access to each APD attached to the circuit through a connected network such as RF wireless and/or Ethernet. By using the Zynq-7000 SoC which has space compatibility [14], our design is also suitable for nano-satellite applications with size/volume constraints and strict SWAP (size-weight-areapower) budgets.…”

Section: Introductionmentioning

confidence: 99%

Realizing a robust, reconfigurable active quenching design for multiple architectures of single-photon avalanche detectors

Sachidananda

Gundlapalli

Leong

et al. 2022

Photonic Instrumentation Engineering IX

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Most active quench circuits used for single-photon avalanche detectors are designed either with discrete components which lack the flexibility of dynamically changing the control parameters, or with custom ASICs which require a long development time and high cost. As an alternative, we present a reconfigurable and robust hybrid design implemented using a System-on-Chip (SoC), which integrates both an FPGA and a microcontroller. We take advantage of the FPGA's speed and configuration capabilities to vary the quench and reset parameters dynamically over a large range, thus allowing our circuit to operate with a wide variety of APDs without having to re-design the system. The microcontroller enables the remote adjustment of control parameters and re-calibration of APDs in the field. The ruggedized design uses components with space heritage, thus making it suitable for space-based applications in the fields of telecommunications and quantum key distribution (QKD). We characterize our circuit with a commercial APD cooled to -20°C, and obtain a deadtime of 35ns while maintaining the after-pulsing probability at close to 3%. We also demonstrate versatility of the circuit by directly testing custom fabricated chip-scale APDs, which paves the way for automated wafer-scale testing and characterization.

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“…The parameters and specify the area requirement of a task. , specifies a column on the target chip such that the next ( − 1) contiguous columns to the right of is the matching position for the task on an intended heterogeneous chip with the optimum number of locations on the chip.This parameter makes the model applicable for heterogeneous tasks and chips.To illustrate this step, the resource utilization of the data processing tasks of a NASA JPL spectrometer application developed in[105] on Xilinx's xc7z100ffg900-2 FPGA chip (shown inTable 4.1) was fed into Algorithm 4.1.…”

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confidence: 99%

“…The top 3 rows (row 0 to 2, with a read border infigure 5) of the chip is reserved for the static region due to the large IO requirement of the DMA engine. The other rows (row 3 to 6) is reserved as reconfigurable region and is shown hosting the data processing tasks of the NASA JPL spectrometer application The details of the application can be found in[105] and[121]. The tasks have been shown in their initial placement location on the chip with empty area for relocation in the case of permanent faults.…”

mentioning

confidence: 99%