Total ionizing dose effects on ring-oscillators and SRAMs in a commercial 28 nm CMOS technology

Abstract

A test chip with 368 ring-oscillators and 4 different SRAMs has been designed to study the effect of total ionizing dose on a commercial 28 nm CMOS technology. The chip has been exposed to 1 Grad(SiO2), followed by a week of annealing at T = 100 °C. The results will be compared to those obtained on single (i.e., isolated) devices in the same 28 nm process and on a similar chip in 65 nm CMOS technology. This test confirms the robustness of the 28 nm technology to ionizing radiation, enabling the development of ASICs capable of surviving in environments with hundreds of Mrad.

Measurements of total ionizing dose effects in TPSCo 65 nm and influence of NMOS bulk bias

“…This leads to assume that transistors with high nominal pre-radiation leakage current will see a lower increase in I sat OFF than transistors with a smaller initial leakage current. Nevertheless it is not possible to correlate the increase of I sat OFF with the length of the transistor, as it could be expected from previous studies [13]. Regarding the post-annealing values, there seems to be a good recovery of the leakage current values, almost going back to their pre-radiation nominal values before TID exposure.…”

X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits

“…These damages are resulting from the generation of electron-hole (eh) pairs in oxides during irradiation [19], [22], [24], [25], [28]. Auxiliary oxides such as shallow-trench-isolation (STI) and spacer oxides are thought to be responsible for Total Inoization Dos -induced performance degradation of modern CMOS-ICs [21].…”

“…These studies are not attacks focused on a transistor and X-rays are either used as a means of inspection or retro-design or to study the harmful effects of irradiation [20] . It is within this framework that attacks are performed with the nano-focused beam from the ESRF on current technology nodes such as 28 nm technologies (the last planar technologies before the FinFETs [21] ). It is possible to quantify the needed doses to fault semi-permanently a single transistor, in many parts of the IC, registers, SRAM or FLASH memories.…”

Dual use driver for high speed links transmitters in the future high energy physics experiments

“…Each transmitter consists of a data generator, scrambler, forward error correction, serializer, output driver and a phase-locked loop (PLL). Radiation tolerant design techniques were implemented in the DART28 design [5][6][7].…”