Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design

Krishnamoorthy, Karthik; Maruvada, S.C.; Balasa, Florin

doi:10.1109/iscas.2007.378437

Cited by 22 publications

(22 citation statements)

References 9 publications

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“…Optimization algorithms translate the design problem into an abstract model and search for an optimal solution regarding specific aims and constraints. When applied to analog layout, suchlike approaches usually focus on one specific design step (particularly placement, as in [4] and [5], and routing, as in [6] and [7]) and its respective difficulties. Relatively few works, such as [8] and [9], deal with the challenge of handling these two heavily correlated tasks simultaneously.…”

Section: A Optimization Algorithmsmentioning

confidence: 99%

“…Amongst others, particular attention lies on abstract floorplan models such as TCG-S [4], sequence pairs [5], [9] and [10] and more enhanced representations [11]. Particular research effort is spent on the formal, explicit consideration of constraints.…”

Section: A Optimization Algorithmsmentioning

confidence: 99%

“…Particular research effort is spent on the formal, explicit consideration of constraints. E.g., for placement many algorithms take device symmetry [5] and [11] and device proximity [10] and [14] into account. For routing, the constraints of interest include net shielding [6] and wiring symmetry [8].…”

Section: A Optimization Algorithmsmentioning

confidence: 99%

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SWARM: A Self-Organization Approach for Layout Automation in Analog IC Design

Marolt¹,

Scheible²,

Jerke³

et al. 2016

IJEEE

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Abstract-Optimization-based analog layout automationdoes not yet find evident acceptance in the industry due to the complexity of the design problem. This paper presents a Self-organized Wiring and Arrangement of Responsive Modules (SWARM), able to consider crucial design constraints both implicitly and explicitly. The flexibility of algorithmic methods and the expert knowledge captured in PCells combine into a flow of supervised module interaction. This novel approach targets the creation of constraintcompliant layout blocks which fit into a specified zone. Provoking a synergetic self-organization, even optimal layout solutions can emerge from the interaction. Various examples depict the power of that new concept and the potential for future developments.  Index Terms-analog IC design, layout automation, constraint engineering, methodology, algorithm, particle system

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Section: A Optimization Algorithmsmentioning

confidence: 99%

Section: A Optimization Algorithmsmentioning

confidence: 99%

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SWARM: A Self-Organization Approach for Layout Automation in Analog IC Design

Marolt¹,

Scheible²,

Jerke³

et al. 2016

IJEEE

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“…Lin et al [15] also presented the symmetric-feasible conditions for the TCG-S representation. Three more recent works [16]- [18] further took advantage of the symmetric-feasible condition in SPs [8]. Koda et al [16] proposed a linear-programming-based method, and Tam et al [17] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible SP.…”

Section: A Previous Workmentioning

confidence: 99%

“…Koda et al [16] proposed a linear-programming-based method, and Tam et al [17] introduced a dummy node and additional constraint edges for each symmetry group after obtaining a symmetric-feasible SP. Krishnamoorthy et al [18] proposed an O(m · n lg lg n) packing-time algorithm by employing the priority queue, where m is the number of symmetry groups and n is the number of modules. More recently, Zhang et al [19] further improved the perturbation time of the TCG representation from O(n 2 ) to O(n).…”

Section: A Previous Workmentioning

confidence: 99%

Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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Hierarchical Placement with Layout Constraints

Chang

2010

Analog Layout Synthesis

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Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design

Cited by 22 publications

References 9 publications

SWARM: A Self-Organization Approach for Layout Automation in Analog IC Design

SWARM: A Self-Organization Approach for Layout Automation in Analog IC Design

Analog Placement Based on Symmetry-Island Formulation

Hierarchical Placement with Layout Constraints

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