Proceedings of CICC 97 - Custom Integrated Circuits Conference
DOI: 10.1109/cicc.1997.606593
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Cited by 19 publications
(13 citation statements)
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“…Fortunately, today, there already exists a number of quality works on the generation of timing abstraction of IP blocks or macros. Some notable works are reported in [2]- [8].…”
Section: Introductionmentioning
confidence: 99%
“…Fortunately, today, there already exists a number of quality works on the generation of timing abstraction of IP blocks or macros. Some notable works are reported in [2]- [8].…”
Section: Introductionmentioning
confidence: 99%
“…In either case, the grey-box model has the disadvantage of exposing the circuit's structure and complexity to higher levels of analysis which is potentially inefficient as well as inapplicable in cases where no part of the intellectual property can be revealed. In contrast, our approach is a black-box type of modeling, based on a technique called clock modeling originally proposed in [6]. Through processing of the internal timing constraints, the clock modeling approach reduces all the timing constraints of a sequential block into a small set of constraints in terms of the circuit's clock parameters, those being clock pulse widths and phase separations.…”
Section: Characterization Of Sequential Blocksmentioning
confidence: 99%
“…The limitation of the method described in [6] is that it is based on topological delay analysis. Thus the clock models it produces can be pessimistic because of false paths.…”
Section: Characterization Of Sequential Blocksmentioning
confidence: 99%
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“…There are previous researches dealing with the timing macromodeling of IP blocks, and all of them are based on the concept of path delay [1,2,3,4,5,6]. The simplest of such models is the "pin-to-pin" delay model used to characterize standard cells and other complex combinational circuits.…”
Section: Introductionmentioning
confidence: 99%