TimeCube: A manycore embedded processor with interference-agnostic progress tracking

Abstract

Abstract-Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. This decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing.In this paper we propose Progress Time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce TimeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress Time. Our evaluation shows that a 32-core TimeCube processor can track application progress with less than 1% error even in the presence of a 6× average worst-case slowdown. TimeCube also uses Progress Times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress Time in manycore chips for embedded systems.

Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores

“…Further, these techniques are either dependent on the replacement policy [36,37] or require modifying the cache tag arrays [33,35]. Similarly, cache partitioning techniques [30,29,10,31] incur significant overhead due to larger associative (up to 128/256-way) tag structures, or require modification to the replacement policies to adapt to their needs [31] [30]. From these discussions, we see that a simple, efficient and scalable cache monitoring mechanism is required.…”

“…Cache partitioning techniques [7,8,6,10] focus on allocating fixed-number of ways per set to competing applications. Typically, a shadow tag structure (that exploits stack property of LRU [26]) [6] monitors the application's cache utility by using counters to record the number of hits each recency-position in the LRU stack receives.…”

Quality Time: A simple online technique for quantifying multicore execution efficiency

“…TimeCube [26] tracks application progress using an analytical performance estimation model similar to the one proposed by Solihin et al [27]. These models are able to model minute architectural details such as tracking prefetches, measure memory bandwidth constraints, and cache intricacies such as dirty lines, via mechanisms like those proposed by Kaseridis et al [28].…”

DR-SNUCA: An energy-scalable dynamically partitioned cache

“…DR-SNUCA has physically separated cache-arrays connected through a point-to-point pipelined on-chip memory network, as shown in Figure 2, which are dynamically allocated to applications. We use the cache allocation algorithm presented in TimeCube [4]. When multiple cache-arrays are allocated to an application, they are merged by increasing the number of cache sets allocated to the application while keeping the number of associative ways constant.…”

“…Moreover, it provides no intuition about the benchmarks that we have not included in our evaluation. In order to limit the evaluation space as well as incorporate a structure into our evaluation, we classify our benchmarks by memory characteristics into a three-type taxonomy [4], and then examine runs that include different ratios of the three types. The taxonomy is as follows: An application which sees no drop in miss rate with increasing cache size is a stream application, an application which sees a sudden drop in miss rate with cache size is a cliff application, and an application whose miss rate drops gradually with increasing cache size is a slope application.…”