Through mold vias for stacking of mold embedded packages

Abstract

The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm2. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular moldi- - ng compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes

Dielectric composite material with good performance and process ability for embedding of active and passive components into PCBs

“…The substrate can for instance be a copper clad laminate [5], a reconfigured wafer [6], [7], or a copper foil [3]. The dielectric can be applied by vacuum pressing, lamination, or by using a mold press equipment.…”

“…A resin film with a claimed thickness of up to 200 my was recently reported [12]. The IZM presented an approach towards chip embedding which uses reconfigured wafers [6], [7]. An epoxy mold compound (EMC) which was applied by compression molding served as a dielectric.…”

From wafer level to panel level mold embedding

“…The proof of concept for this technology combination was successfully /done for a 2-chip LGA package [6], for a stackable BGA package [7] as well as for a functional sensor-ASIC package [8]. 24"x18" 12" 8" 6" …”

Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

“…In 3D vertical integration, ultra-thin dies are embedded in build-up layers of a printed circuit board (PCB), as introduced by Fraunhofer IZM [6]. Braun et al [7] combined both concepts which are embedding the dies into polymer and using PCB technology for redistribution. The result is a two-chip land grid array package.…”

“…Nextgeneration eWLB design tends toward double-sided eWLB with vertical interconnections, a multi-layer redistribution layer (RDL) eWLB, a large size eWLB, and multiple chips eWLB [5]. Double-sided eWLB with vertical interconnections, such as TMV, enables the 3D stacking of PoP [7]. The present study proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections.…”