Three-dimensional device simulator Caddeth with highly convergent matrix solution algorithms

Toyabe, T.; Masuda, H.; Aoki, Yumiko; Shukuri, H.; Hagiwara, Takayuki

doi:10.1109/t-ed.1985.22236

Cited by 77 publications

(5 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our new methodology is implemented in the 3D process simulator, SPIRIT-IIIIADL. Our 3D-TCAD system composed of SPIRIT-IIUADL and our in-house device simulator CADDETH3 [4] was applied to the design of 3D-shaped power MOSFETs [5] and we confirmed that this TCAD system can be efficiently applied.…”

Section: Introductionmentioning

confidence: 82%

A Very Fast Three-Dimensional Impurity Profile Simulation Incorporating An Accumulated Diffusion Length and Its Application to the Design of Power MOSFETs

Kamohara

Sugaya

Matsuo

1995

Simulation of Semiconductor Devices and Processes

View full text Add to dashboard Cite

b~entral ~e i e a r c h ~a b o r a t o j , ~i t a c h i , Ltd., -1-280, Higashi-koigakubo Kokubunji, Tokyo 185, Japan AbstractIn this paper, we introduce a method for the fast simulation of 3D impurity profile simulation We analytically integrated the approximated non-linear transport equation and derived an analytical equation of 3D non-linear diffusion by introducing a new physical parameter, called the Accumulated Diffusion Length (ADL). This method allows us to simulate a 3D-profile by using a coupled 1D simulator and analytical equations, where the ADL is obtained during 1D simulation. Our new methodology is implemented in the 3D process simulator, SPIRIT-IWADL. Our 3D-TCAD system composed of SPIRIT-IIIIADL and our in-house device simulator was applied to the design of 3D-shaped power MOSFETs.

show abstract

Section: Introductionmentioning

confidence: 82%

A Very Fast Three-Dimensional Impurity Profile Simulation Incorporating An Accumulated Diffusion Length and Its Application to the Design of Power MOSFETs

Kamohara

Sugaya

Matsuo

1995

Simulation of Semiconductor Devices and Processes

View full text Add to dashboard Cite

show abstract

“…The electric field, F, is the maximum electric field around the gate edge obtained by carrying out three-dimensional (3D) device simulator with CADDETH. 24) Figure 3 shows the comparison between the model and the experimental results of the leakage current, I L , as the function of V j . For model calculations, we use the values as T ¼ 85 C, E t ¼ 0:62 eV, and F from the device simulation.…”

Section: Modeling Of the Leakage Currentmentioning

confidence: 99%

Statistical p–n Junction Leakage Model via Trap Level Fluctuation for Refresh-Time-Oriented Dynamic Random Access Memory Design

Kamohara

Kubota

Moniwa

et al. 2008

jjap

View full text Add to dashboard Cite

We have developed a new model for the leakage current of a single tail bit of dynamic random access memories (DRAMs). This model can explain the leakage current of each tail bit quantitatively. To derive model equations, we assume that some bits containing one specific trap center become tail bits among all bits in a DRAM chip. The variation of the leakage current of tail bits is attributed to the fluctuation of the trap level. Extracted value of the average trap level is 0.677 eV, which is the close value of the trap centers generated by Cu and Fe. By introducing the trap level fluctuation model, we have successfully reproduced the distribution of the retention time for tail bits. We also have obtained a good agreement between model and experimental results of tail distributions as functions of process splits and the temperature by using the present model. As an example applied by the present model, we estimated the required number of the repairable bits for 1 Gbyte DRAM.

show abstract

“…The simulation results by a three device simulator are compared with electron which should is iniected into the floating g'ate. The potential and electric field distribution in the channel reg:ion of FIB-EPROM device are simulated by the three dimensional device simulator, CADDETH (4).…”

Section: Imens Ionalmentioning

confidence: 99%

A Novel EPROM Device Using Focused Boron Ion Beam Implantation

Shukuri¹,

Wada²,

Komori³

et al. 1986

Extended Abstracts of the 1986 International Conference on Solid State Devices and Materials

View full text Add to dashboard Cite

A novel FAIvIOS type EPROM device is demonstrated, which has a heavily focused ion beam implanted region at the drain edge of the channel reSlion. This heavily doped region permits higher electric field near the drain edge, resulting: in remarkable increase of hot-carrier g:eneration tate, which reduces both the progranming voltage and programmin8i time. Three dimensional device simulator, CADDETIL predicted the device characteristics fairly wel1. programming time of a fabricated device with effective channel width of 3.1 !rm is 5oms, which is 1,250 of that of a conventional device' B-7-5

show abstract

Three-dimensional device simulator Caddeth with highly convergent matrix solution algorithms

Cited by 77 publications

References 15 publications

A Very Fast Three-Dimensional Impurity Profile Simulation Incorporating An Accumulated Diffusion Length and Its Application to the Design of Power MOSFETs

A Very Fast Three-Dimensional Impurity Profile Simulation Incorporating An Accumulated Diffusion Length and Its Application to the Design of Power MOSFETs

Statistical p–n Junction Leakage Model via Trap Level Fluctuation for Refresh-Time-Oriented Dynamic Random Access Memory Design

A Novel EPROM Device Using Focused Boron Ion Beam Implantation

Contact Info

Product

Resources

About