Thermomechanical and electrochemical reliability of fine-pitch through-package-copper vias (TPV) in thin glass interposers and packages

Demir, Kaya; Ramachandran, Koushik; Sato, Yoichiro; Qiao, Chunming; Sukumaran, Vijay; Pucha, Raghuram V.; Sundaram, Venkatesh; Tummala, Rao

doi:10.1109/ectc.2013.6575595

Cited by 19 publications

(3 citation statements)

References 12 publications

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“…Moreover, the CTE of glass material can also be selected to satisfy different package structure requirement [3]. The thermal, mechanical, and reliability of glass had also been demonstrated [4]. Advanced applications such as Cu Microwire Arrays also have been addressed [5].…”

Section: Introductionmentioning

confidence: 98%

Embed glass interposer to substrate for high density interconnection

Hu¹,

Hung²,

Chen³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Current organic substrates are limited to lines/space 10/10 μm and via size around 50 μm. However, the semiconductor with advance node needs fine line/space of 5/5 or 3/3 and even 2/2 μm in the future. Interposer provides a high density interconnection with fine line and small via that cannot be matched by current laminate substrate technology. We have proposed a new structure that embedded interposer to organic substrate (Flip chip -Embedded Interposer Carrier, FC-EIC ® ). This structure has virtues of know good substrate and compatible with current packaging and assembly infrastructure. We have demonstrated the feasibility of integrating silicon interposer to a laminate substrate.In this paper, we evaluated the feasibility of integration of a glass interposer into an organic substrate. The selection of glass, temporary bonding materials and built-up dielectric materials were established. The compatibility of lamination and built-up process with glass interposer was demonstrated. By using dielectric materials with small CTE and high modules together with an innovative structure, significant warpage reduction of the EIC-glass was achieved. For a 10 cm x 10 cm laminated carrier with a proper dielectric material set, the panel warpage of the EIC-glass structure can be reduced from 20 mm to less than 3 mm. The EIC-glass structure has been tested under 500 TCT cycles and no glass damage and delamination between glass and the built-up dielectric film was observed. IntroductionSemiconductor technology is rapidly moving from 28 nm to 20 nm and even to 16 nm nodes. However the organic substrate, which is widely used as a substrate for silicon chips, is difficult to match the line shrinking speed of the semiconductor. Current organic substrate can support circuit pattern of line/space of 10/10 μm, but the industry is looking for line/space of 5/5 μm and even in some case 2/2 μm in the future. The material and tools to support this fine line in organic substrate is under intense development in the industry.But for semiconductor industry, the infrastructure of fine lines and small vias are already there. 2.5D and 3D packaging integration using semiconductor technology and silicon are under intense development. Silicon interposer can meet fine line/space requirement easily by means of wafer level processes. However, the cost of processing is very high. This prevents the wide use of silicon interposer. We have proposed a new FC-EIC ® structure which embedded the interposer to an organic substrate in ECTC 2013 [1]. The EIC structure has lower profile and possible better electrical performance by eliminating the solder joints between the interposer and the organic substrate. The integration of silicon interposer and

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Section: Introductionmentioning

confidence: 98%

Embed glass interposer to substrate for high density interconnection

Hu¹,

Hung²,

Chen³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…An essential component that enables the glass interposer is the Cu filled through-glass via (TGV), which provides vertical electrical connections and facilitates heat dissipation in the 2.5DICs (Demir et al, 2013;Horibe et al, 2015;Malta et al, 2010). The fabrication process of TGVs involves drilling of through holes in the thin glass substrate and filling of the vias with Cu by electroplating (Sukumaran et al, 2014;Sukumaran et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

“…As a result, interfacial delamination, while scant in TSVs, is a critical concern for TGVs. Although numerous studies are available on the thermomechanical reliability of TSVs (Ding et al, 2014;Tsai et al, 2012;Okoro et al, 2010;Xi et al, 2009;Ryu et al, 2011;Lee et al, 2011;Jiang et al, 2013;Lu et al, 2009), very few studies have been conducted on the reliability of TGVs, and none on the interfacial reliability (Viswanathan et al, 2017;Demir et al, 2013;Ching-Kuan et al, 2016;Demir et al, 2017). To develop a reliable glass-based interposer technology and reveal the impact of design and material selections, a thorough and comprehensive analysis of the interfacial reliability of TGVs is important and much needed.…”

Section: Introductionmentioning

confidence: 99%

The interfacial reliability of through-glass vias for 2.5D integrated circuits

Ahmed

Jalilvand

Pollard

et al. 2020

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Purpose Glass is a promising interposer substrate for 2.5 D integration; yet detailed analysis of the interfacial reliability of through-glass vias (TGVs) has been lacking. The purpose of this paper is to investigate the design and material factors responsible for the interfacial delamination in TGVs and identify methods to improve reliability. Design/methodology/approach The interfacial reliability of TGVs is studied both analytically and numerically. An analytical solution is presented to show the dependence of the energy release rate (ERR) for interfacial delamination on the via design and the thermal mismatch strain. Then, finite element analysis (FEA) is used to investigate the influence of detailed design and material factors, including the pitch distance, via aspect ratio, via geometry and the glass and via materials, on the susceptibility to interfacial delamination. Findings ERR for interfacial delamination is directly proportional to the via diameter and the thermal mismatch strain. Thinner wafers with smaller aspect ratios show larger ERRs. Changing the via geometry from a fully filled via to an annular via leads to lower ERR. FEA results also show that certain material combinations have lower thermal mismatch strains, thus less prone to delamination. Practical implications The results and approach presented in this paper can guide the design and development of more reliable 2.5 D glass interposers. Originality/value This paper represents the first attempt to comprehensively evaluate the impact of design and material selection on the interfacial reliability of TGVs.

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