2017 IEEE Energy Conversion Congress and Exposition (ECCE) 2017
DOI: 10.1109/ecce.2017.8096674
|View full text |Cite
|
Sign up to set email alerts
|

Thermal stress mitigation by Active Thermal Control: Architectures, models and specific hardware

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
4
0

Year Published

2018
2018
2023
2023

Publication Types

Select...
3
3
1

Relationship

2
5

Authors

Journals

citations
Cited by 15 publications
(5 citation statements)
references
References 12 publications
0
4
0
Order By: Relevance
“…Experimental data showing the closed loop limitation of the junction temperature have been presented. However thanks to the high level of dynamic of the proposed method, it is possible to implement more sophisticated techniques like the one presented in [16] - [18], that actively reduce the temperature swing of the component and permits to extend the lifetime of the semiconductor.…”
Section: Active Thermal Controlmentioning
confidence: 99%
“…Experimental data showing the closed loop limitation of the junction temperature have been presented. However thanks to the high level of dynamic of the proposed method, it is possible to implement more sophisticated techniques like the one presented in [16] - [18], that actively reduce the temperature swing of the component and permits to extend the lifetime of the semiconductor.…”
Section: Active Thermal Controlmentioning
confidence: 99%
“…‚ Improving the reliability of operation close to thermal restrictions ‚ Achieving a more reasonable difference between the maximum junction temperature throughout the operation and the nominal junction temperature ‚ Enhancing the operation performance during transient at thermal restrictions Decrease in thermal cycle Manipulation in terms of the following: -Switching power loss: • Gate resistance ( [210], [223], [224]), • Frequency ( [27], [28], [45], [46], [216], [210], [225], [226], [227], [228], [229]), • Gate drivers ( [32], [230], [222], [231], [232], [233], [234], [235]), • Shoot-through duty ratio ( [233]).…”
Section: E Cost Analysismentioning
confidence: 99%
“…In fact, the choice of a specific chip carrier (package) imposes a limit on the maximum power loss that can be dissipated by the device (P max ). Consequently, the conduction loss must be lower than the fraction (1 − r)P max , where r is the loss distribution coefficient (LDC), describing the ratio between switching power loss and total device loss [10]:…”
Section: On-state Drain-source Voltage As a Tsepmentioning
confidence: 99%