Theoretical investigation of surface roughness scattering in silicon nanowire transistors

Wang, Jing; Polizzi, Eric; Ghosh, Avik W.; Datta, Supriyo; Lundstrom, Mark

doi:10.1063/1.2001158

Cited by 144 publications

(110 citation statements)

References 14 publications

Supporting

Mentioning

106

Contrasting

Order By: Relevance

“…The electron density is used to calculate, self-consistently, the electrostatic potential through the Poisson's equation. The obtained solutions of the NEGF and Poisson equations are iterated in a Gummel-like loop until density and current converge [10][11][12].…”

Section: Simulation Methodologymentioning

confidence: 99%

Metamorphosis of a nano wire: A 3-D coupled mode space NEGF study

Amoroso

Georgiev

Towie

et al. 2014

2014 International Workshop on Computational Electronics (IWCE)

View full text Add to dashboard Cite

. Abstract-In this paper we present a 3D coupled mode space NEGF study of the quantum features of a nanoscale Gate-AllAround (GAA) silicon transistor. The bottom oxide of the structure is parameterized in order to progressively transform the nanowire in a tri-gate FinFET and the electron transport studied for several Fin widths, back-biases voltages and electron effective masses. Moreover, we address in detail the treatment of the boundary conditions at the channel interface to model the wave function penetration into the gate oxide. We report quantitative results of the charge density obtained by a simplified and a complete discretization approach.

show abstract

Section: Simulation Methodologymentioning

confidence: 99%

Metamorphosis of a nano wire: A 3-D coupled mode space NEGF study

Amoroso

Georgiev

Towie

et al. 2014

2014 International Workshop on Computational Electronics (IWCE)

View full text Add to dashboard Cite

show abstract

“…11,22 In these devices it is observed that surface roughness and channel shape can strongly affect device performance. 23 A highly isotropic, chemically driven etch is required for this undercut and, because the channel is exposed, it must have extremely high selectivity for the buffer relative to the channel. At very small dimensions below the gate wet etching can encounter challenges with the reliability of the etch due to limited flow in tight spaces affecting etchant diffusion as well as released channel collapse or incomplete etchant removal due to capillary force from an aqueous cleaning solution.…”

Section: Potential Applications For Atomic Layer Etchingmentioning

confidence: 99%

Atomic Layer Etching: An Industry Perspective

Carver

Plombon

Romero

et al. 2015

ECS J. Solid State Sci. Technol.

143

128

View full text Add to dashboard Cite

This paper provides an industry perspective on atomic layer etching (ALEt) process. Two process sequences representing two different methods of ALEt are described, followed by several examples where ALEt can be an enabling process technology in the semiconductor industry. The authors believe that there needs to be an increased understanding of surface functionalization, modification and chemistry-based material removal. We are confident that this review article will allow for increased scientific and technological solutions for enabling ALEt.

show abstract

“…[4] For doped Si NW with radius of 5-60 nm the resistivity increased due to change in the impurity activation energy by the quantum confinement effects. [18] In our case, for the undoped NW with a cross section of 2020 nm 2 , reduction of width by ultrathin oxide is less than 1 nm, therefore, such effect is insignificant.…”

Section: Current Calculationsmentioning

confidence: 99%

“…Of particular attention is the role of surface and interface properties in carrier transport in advanced Si nanowire (NW) devices. [1][2][3][4] Scanning probe techniques such as scanning spreading resistance microscopy (SSRM), scanning Kelvin probe microscopy (SKPM) have been employed for two-dimensional (2D) characterization of modern devices. However, high load from the SSRM probe and the series resistance have become the limitation for quantitative characterization of nanowire devices smaller than 50 nm.…”

Section: Introductionmentioning

confidence: 99%

Nanoscale Characterization of Silicon-On-Insulator Nanowires by Multimode Scanning Probe Microscopy

Bolotov

Tada

Morita

et al. 2013

Trans. Mat. Res. Soc. Japan

View full text Add to dashboard Cite

Structural and electronic properties of silicon-on-insulator (SOI) nanowires with a cross section area of 2020 nm 2 were investigated with high spatial resolution by multimode scanning probe microscopy (MSPM) in the constant force mode. The position-dependent tunneling current was measured in the interior of the Si nanowires whose surfaces were terminated with hydrogen and with ultrathin thermal oxide. The current value and fluctuations were reduced for Si nanowires terminated with an ultrathin oxide layer (~0.3 nm), indicating the homogeneous surface passivation. The tunneling current decreased within a distance of ~300 nm from the Si pad electrode for both types of surface termination. Calculations of the tunneling current were performed based on the macroscopic conduction model including the conductance contributions of the nanowire volume and the surface states. In the model, the bulk carrier concentration and the surface state density were tuned to fit the experimental data for the small Si nanowires. The results support the length-dependent conductance of thin Si nanowires, demonstrating the ability of the technique for characterization of modern silicon-on-insulator devices.

show abstract

Theoretical investigation of surface roughness scattering in silicon nanowire transistors

Cited by 144 publications

References 14 publications

Metamorphosis of a nano wire: A 3-D coupled mode space NEGF study

Metamorphosis of a nano wire: A 3-D coupled mode space NEGF study

Atomic Layer Etching: An Industry Perspective

Nanoscale Characterization of Silicon-On-Insulator Nanowires by Multimode Scanning Probe Microscopy

Contact Info

Product

Resources

About