The VLSI-programming language Tangram and its translation into handshake circuits

Berkel, Kees van; Kessels, J.; Roncken, Marly; Saeijs, R.; Schalij, F.

doi:10.1109/edac.1991.206431

Cited by 113 publications

(56 citation statements)

References 10 publications

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“…One such tool which have recently been made commercially available is the Haste design language and the associated TiDE design environment from Handshake Solutions [5]. The tool was formerly known under the name Tangram [13], [14]. Figure 1(a) shows the Haste/TiDE design flow.…”

Section: Extending Syntax-directed-translationmentioning

confidence: 99%

Current trends in high-level synthesis of asynchronous circuits

Sparsø

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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Abstract-This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e.g. the Haste/TiDE tool from Handshake Solutions or the Balsa tool from the University of Manchester. The aims are to add highlevel synthesis capabilities to these tools and to extend the tools such that a wider range of (higher speed) micro-architectures can be generated. Another branch of research takes a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly continuoustime asynchronous circuits that operate without a clock. The perspective here is that the substitution/conversion is done as the final step in an otherwise conventional synchronous design flow.

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Section: Extending Syntax-directed-translationmentioning

confidence: 99%

Current trends in high-level synthesis of asynchronous circuits

Sparsø

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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“…As the design methods for asynchronous circuits, handshake-component-based design [1] was proposed. In handshake-component-based design, asynchronous circuits are designed by connecting handshake components.…”

Section: Introductionmentioning

confidence: 99%

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Yoshiya

Hariyama

Kameyama

2013

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.

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“…$5.00 flows based on SYSTEMC 2 or COWARE 3 , hardware compilers based on process calculi (e.g. [33,30]), or higher-order structural languages such as LAVA [5]; these are interesting and useful, but conceptually different ways of approaching VLSI design.…”

Section: Introductionmentioning

confidence: 99%

Function interface models for hardware compilation

Ghica¹

2011

Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)

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The problem of synthesis of gate-level descriptions of digital circuits from behavioural specifications written in higherlevel programming languages (hardware compilation) has been studied for a long time yet a definitive solution has not been forthcoming. The argument of this essay is mainly methodological, bringing a perspective that is informed by recent developments in programming-language theory. We argue that one of the major obstacles in the way of hardware compilation becoming a useful and mature technology is the lack of a well defined function interface model, i.e. a canonical way in which functions communicate with arguments. We discuss the consequences of this problem and propose a solution based on new developments in programming language theory. We conclude by presenting a prototype implementation and some examples illustrating our principles.

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The VLSI-programming language Tangram and its translation into handshake circuits

Cited by 113 publications

References 10 publications

Current trends in high-level synthesis of asynchronous circuits

Current trends in high-level synthesis of asynchronous circuits

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Function interface models for hardware compilation

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