The Strong correlation Between Code Signatures and Performance

Lau, Jeremy; Sampson, John J.; Perelman, Erez; Hamerly, Greg; Calder, Brad

doi:10.1109/ispass.2005.1430578

Cited by 65 publications

(36 citation statements)

References 19 publications

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“…If the distance between the two BBVs is small (close to 0), then the two intervals spend about the same amount of time in roughly the same code, and therefore we expect the performance of those two intervals to be similar. Code signatures grouped into the same cluster have been shown to exhibit similar CPI, numbers of branch mispredictions, numbers of cache misses, etc [10,14].…”

Section: Simpointmentioning

confidence: 99%

Considering all starting points for simultaneous multithreading simulation

Biesbrouckt¹,

Eeckhout²,

Calder³

2006 IEEE International Symposium on Performance Analysis of Systems and Software

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Section: Simpointmentioning

confidence: 99%

Considering all starting points for simultaneous multithreading simulation

Biesbrouckt¹,

Eeckhout²,

Calder³

2006 IEEE International Symposium on Performance Analysis of Systems and Software

Self Cite

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“…Application runtime, measured in instructions, is on the horizontal axis; the vertical axis represents the offset d. Light colors denote a low similarity between the BBVs at a given point in the program with those a distance d away, whereas dark colors denote strong correlation -which implies similar execution behavior [14]. In this case, we can see that the N-ft benchmark, running the class A input set with 8 threads, has one periodicity at 550k instructions that occurs for a part of the application runtime, and another which occurs at 1.14M instructions and exists during the entire application execution.…”

Section: B Determining Application Periodicitymentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

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“…BBV similarity is quantified by computing the Manhattan distance between two BBVs. The intuitive notion is that intervals of execution with similar code signatures have similar architectural behavior, and this has been shown to be the case by Lau et al [21]. Therefore, only one interval from each phase needs to be simulated in order to recreate an accurate picture of the entire program execution.…”

Section: Representative Samplingmentioning

confidence: 99%

Finding Stress Patterns in Microprocessor Workloads

Vandeputte

Eeckhout

2009

High Performance Embedded Architectures and Compilers

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Abstract. Power consumption has emerged as a key design concern across the entire computing range, from low-end embedded systems to high-end supercomputers. Understanding the power characteristics of a microprocessor under design requires a careful study using a variety of workloads. These workloads range from benchmarks that represent typical behavior up to hand-tuned stress benchmarks (so called stressmarks) that stress the microprocessor to its extreme power consumption. This paper closes the gap between these two extremes by studying techniques for the automated identification of stress patterns (worst-case application behaviors) in typical workloads. For doing so, we borrow from sampled simulation theory and we provide two key insights. First, although representative sampling is slightly less effective in characterizing average behavior than statistical sampling, it is substantially more effective in finding stress patterns. Second, we find that threshold clustering is a better alternative than k-means clustering, which is typically used in representative sampling, for finding stress patterns. Overall, we can identify extreme energy and power behaviors in microprocessor workloads with a three orders of magnitude speedup with an error of a few percent on average.

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The Strong correlation Between Code Signatures and Performance

Abstract: A recent study [1]

Cited by 65 publications

References 19 publications

Considering all starting points for simultaneous multithreading simulation

Considering all starting points for simultaneous multithreading simulation

Sampled simulation of multi-threaded applications

Finding Stress Patterns in Microprocessor Workloads

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