The scaling of electromigration lifetimes

Oates, A. S.; Lin, Ming‐Hsien

doi:10.1109/irps.2012.6241868

Cited by 28 publications

(15 citation statements)

References 13 publications

(13 reference statements)

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“…We have shown that void volumes measured during accelerated testing are independent of technology nodes 65 to 20 nm despite significant changes in the Cu microstructure in this range. 2 Therefore, failure times are controlled primary by the Cu drift velocity, which is determined by the nature of the diffusion pathways for the conductor, and is, therefore, sensitive to the details of the Cu microstructure. In the next section we discuss in detail how the Cu microstructure determines the drift velocity.…”

Section: Influence Of Cu Microstructure On Electromigration Failurementioning

confidence: 99%

Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm

Oates

2014

ECS J. Solid State Sci. Technol.

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A key element for future silicon IC technology development is the containment of electromigration -induced failure of Cu / low-k interconnects. Continued progress in meeting electromigration reliability requirements for future technology nodes will require a multi-faceted approach to the problem: first the development of effective process solutions to limit the impact of technology scaling on electromigration life-time reduction; and second, the provision of models of failure that are representative of circuit operation to determine realistic current-limiting design rules. We will show that process solutions involve limiting the rate of transport along interfaces and grain boundaries in the damascene trench architecture using metal capping layers and Cu alloys. Most models of electromigration failure have been developed using DC stress conditions, while circuits predominantly operate with non-DC (pulsed DC or AC) signals. Understanding the relationship between failure under DC and non-DC conditions is a necessary aspect of realistic reliability characterization. In this paper we review: our recent studies that establish the relationship between Cu microstructure, metallic capping and dilute Cu alloy additions and thereby identify effective scenarios for mitigation with technology scaling; and experimental studies of electromigration failure under non-DC stress that explore the physical mechanisms involved. Electromigration failure of interconnects has been a long-standing concern for the development of highly reliable integrated circuits (IC). Despite intense efforts following the first observation of electromigration -related failure of Al circuit interconnects in 1966, 1 it has proven impossible to find a robust process solution by material modification for either Al or the more recently introduced Cu metal system. It remains an issue that can only be partially mitigated with process solutions, and ultimately it is controlled at the circuit level by the use of current limiting design rules. There is a prevalent concern that this method of control of the rate of electromigration failure will be detrimental to circuit performance. Therefore, during technology development, a balance must be found to ensure circuit performance is maintained without seriously impairing electromigration reliability. Achieving this balance requires a thorough fundamental understanding of the factors that determine the efficacy of process mitigation techniques. Moreover, current limiting design rules are extrapolated from accelerated test data using models of the failure mechanism, and the models must accurately reflect the physical mechanisms of failure.For the most advanced Si process technologies currently being manufactured with Cu and low-k dielectrics, electromigration failure times have decreased rapidly with technology progression, adding urgency to the problem of assuring electromigration reliability. Fig. 1 shows the reduction in failure time for both long conductor lengths and for shorter lengths; 2,3 for the latter, the Bl...

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Section: Influence Of Cu Microstructure On Electromigration Failurementioning

confidence: 99%

Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm

Oates

2014

ECS J. Solid State Sci. Technol.

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“…4. Unlike the typically observed slit void failure mode [10][11][14][15][16][17] from downstream EM test, physical failure analysis revealed trench void for both downstream and upstream stress, as shown in Fig. 5.…”

Section: Resultsmentioning

confidence: 83%

Study of a new electromigration failure mechanism by novel test structure

Chen

Lin

Hsieh

et al. 2015

2015 IEEE International Reliability Physics Symposium

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A novel electromigration (EM) structure is designed and characterized with advanced Cu/low-k technology. Comparing the EM results derived from novel and traditional test structures, a new EM failure mechanism is proposed. The new mechanism is caused by the Cu/barrier interface damage at the metal line-edge during upper Via opening process. This damage provides a fast diffusion path. From the downstream EM test, it is observed that the thicker Ta-based ALD barrier has a higher activation energy and median time to failure compared to thinner Ta based barrier. Thicker barrier process enhances Cu/barrier adhesion and hence prevent the via opening induced interface damage.

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“…Due to the decrease of critical feature size with scaling, as well as changes in the microstructure of the Cu, failure times have decreased significantly with technology scaling [76][77][78]. This reduction poses a serious challenge to attaining the increasing current densities required for continued performance enhancement and density increase.…”

Section: Electromigrationmentioning

confidence: 99%