The Raw microprocessor: a computational fabric for software circuits and general-purpose programs

Taylor, Michael; Kim, J.; Miller, Joel B.; Wentzlaff, David; Ghodrat, F.; Greenwald, Bruce C.; Hoffman, Henry; Johnson, Paul R.; Lee, Jae‐Wook; Lee, W.; Ma, Albert; Saraf, Arvind; Seneski, M.; Shnidman, Nathan; Strumpen, Volker; Frank, Matthew I.; Amarasinghe, Saman; Agarwal, Anant

doi:10.1109/mm.2002.997877

Cited by 739 publications

(312 citation statements)

References 6 publications

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“…Therefore, it is expected that future CMPs will be designed as arrays of replicated tiles connected over a switched direct network [23,28]. In these architectures, the design of the on-chip interconnection network has proven to have a significant impact on overall system performance and energy consumption, since it is implemented using global wires that show long delays and high capacitance properties.…”

Section: Introductionmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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Continuous improvements in integration scale have made possible the inclusion of several processor cores on the same chip. Such designs have been named chip-multiprocessors (or CMPs) and constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and increasing number of transistors available on a single chip have revealed energy consumption as a critical design issue in current and future microarchitectures. In these architectures, the design of the on-chip interconnection network has proven to have significant impact on overall system performance and energy consumption, and that the wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.In this work, we present a detailed characterization of the energy-efficiency of a CMP for parallel scientific applications using Sim-PowerCMP, a detailed architectural-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, Hot Leakage and Orion) into a single framework that allows precise analysis and optimization of power dissipation (both dynamic and static) taking into account performance. In this characterization, we pay special attention to the energy consumed on the interconnection network. Results for an 8-and 16-core CMP show that the most power consuming messages are the replies that carry data (almost 70% on average of the total energy consumed in the interconnect) although they represent 30% of the total number of messages. Furthermore, we show that using on-chip wires with varying latency, bandwidth, and energy characteristics can reduce the energy dissipated by the links of the interconnection network about 65% with an average impact of 10% in the execution time.

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Section: Introductionmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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“…Other examples include the Sun Niagara 2 [24] and the upcoming Intel Many Integrated Core (MIC) architecture. Research machines such as UT Austin's TRIPS [9], MIT's RAW [28] (available commercially as the TILE architecture from Tilera [2]), and UMD's XMT [33,36] are also examples of single-chip many-cores.…”

Section: Fig 1 Miss Handling Architecture (Mha) For a Banked Cache mentioning

confidence: 99%

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

Caragea

Tzannes

Keceli

et al. 2011

Int J Parallel Prog

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Abstract. Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi-and many-cores with shared parallel caches further increase MLP demand. Current cache hierarchies however have been unable to keep up with this trend, with modern designs allowing only 4-16 concurrent cache misses. This disconnect is exacerbated by recent highly parallel architectures (e.g. GPUs) where power and area per-core budget favor numerous lighter cores with less resources, further reducing support for MLP on a per-core basis. Support for hardware and software prefetch increases MLP pressure since these techniques overlap multiple memory requests with existing computation. In this paper, we propose and evaluate a novel Resource-Aware Prefetching (RAP) compiler algorithm that is aware of the number of simultaneous prefetches supported, and optimized for the same. We implemented our algorithm in a GCC-derived compiler and evaluated its performance using an emerging fine-grained many-core architecture. Our results show that the RAP algorithm outperforms a well-known loop prefetching algorithm by up to 40.15% in run-time on average across benchmarks and the state-of-the art GCC implementation by up to 34.79%, depending upon hardware configuration. Moreover, we compare the RAP algorithm with a simple hardware prefetching mechanism, and show run-time improvements of up to 24.61%. To demonstrate the robustness of our approach, we conduct a designspace exploration (DSE) for the considered target architecture by varying (i) the amount of chip resources designated for per-core prefetch storage and (ii) off-chip bandwidth. We show that the RAP algorithm is robust in that it improves performance across all design points considered. We also identify the Pareto-optimal hardware-software configuration which delivers 53.66% run-time improvement on average while using only 5.47% more chip area than the bare-bones design.

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“…A number of possibilities have been suggested ranging from a heterogeneous mixture of logic blocks based on multi-bit functional units including multipliers, memories, and arithmetic logic units (ALUs) [77] to homogeneous mixtures of full processors [192,206]. The original developments in this area favored logic blocks with relatively simple functional unit blocks.…”

Section: Coarse-grained Fpgasmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

294

106

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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The Raw microprocessor: a computational fabric for software circuits and general-purpose programs

Cited by 739 publications

References 6 publications

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

FPGA Architecture: Survey and Challenges

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