The Impact of NBTI on the Performance of Combinational and Sequential Circuits

Wang, Wenping; Yang, Su; Bhardwaj, Sarvesh; Vattikonda, Rakesh; Vrudhula, Sarma; Liu, Frank; Cao, Yu

doi:10.1109/dac.2007.375188

Cited by 86 publications

(90 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Degradation in terms of SNM is not much when v dd reduction is done in standby mode. Experimental results published in [25] shows that under lower v dd , transistors and circuit performance become more sensitive to stress induced v th shift and even a small degradation in v th can result in larger timing degradation.…”

Section: Supply Voltage Reductionmentioning

confidence: 99%

A Review of NBTI Degradation and its Impact on the Performance of SRAM

Dutta

Soni

Pattanaik

2016

IJMECS

View full text Add to dashboard Cite

Abstract-Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.

show abstract

Section: Supply Voltage Reductionmentioning

confidence: 99%

A Review of NBTI Degradation and its Impact on the Performance of SRAM

Dutta

Soni

Pattanaik

2016

IJMECS

View full text Add to dashboard Cite

show abstract

“…More recently researchers have begun to investigate the effect of NBTI on the timing characteristics of flip-flops. In [6] it was claimed that in the presence of NBTI, the setup and hold time of the flip-flops remain nearly constant. In [7], the effect of NBTI on different low power and high performance flip-flops was studied; however, no solution was offered to alleviate the problem.…”

Section: Introductionmentioning

confidence: 99%

Multi-corner, energy-delay optimized, NBTI-aware flip-flop design

Abrishami

Hatami

Pedram

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing the codependent setup and hold time (CSHT) contours. Third, we introduce a multicorner optimization problem to minimize the energy-delay product of the flip-flops. The optimization relies on mathematical programming to find the best transistor sizes. Finally, we apply our proposed optimization formulation on True Single-Phase Clock (TSPC) flip-flops and show the simulation results.

show abstract

“…Letting the device completely wear-out will impact the system as defective cores have to be removed from the pool of active cores. Different from existing approaches [2][3] that focused on long term stress using static NBTI models, we propose to use fractional stress and recovery in the multi-core systems. We model NBTI with regard to threshold voltage changes, and then reflect the threshold variations to timing degradation of the core.…”

Section: Introductionmentioning

confidence: 99%

“…According to [2], the widely different diffusivity of H 2 in the oxide and polysilicon causes PMOS transistors to alternate between stress and recovery. The recovery itself consists of two steps, a fast recovery and a slow recovery.…”

Section: Introductionmentioning

confidence: 99%

NBTI aware workload balancing in multi-core systems

Sun

Kodi

Louri

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

View full text Add to dashboard Cite

Abstract-As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core system that includes device wear-out impact. Based on device fractional NBTI model, we propose a new NBTI aware system workload model, and develop new dynamic tile partition (DTP) algorithm to balance workload among active cores while relaxing stressed ones. Experimental results on 64 cores show that by allowing a small number of cores (around 10%)to relax in a short time period (10 second), the proposed methodology improves CMP system yield. We use the percentage of core failure to represent the yield improvement. The new strategy improves the core failure number by 20 %, and extend MTTF by 30% with little degradation in performance (less than 6%).

show abstract

The Impact of NBTI on the Performance of Combinational and Sequential Circuits

Cited by 86 publications

References 0 publications

A Review of NBTI Degradation and its Impact on the Performance of SRAM

A Review of NBTI Degradation and its Impact on the Performance of SRAM

Multi-corner, energy-delay optimized, NBTI-aware flip-flop design

NBTI aware workload balancing in multi-core systems

Contact Info

Product

Resources

About