The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Wang, Wenping; Yang, Shengqi; Bhardwaj, Sarvesh; Vrudhula, Sarma; Liu, F.; Cao, Yu

doi:10.1109/tvlsi.2008.2008810

Cited by 245 publications

(141 citation statements)

References 21 publications

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“…Thus, it becomes impractical to perform simulation in order to predict ∆V th . However, various recent studies have shown that it is possible to obtain a closed form for the upper bound on the ∆V th as a function of the duty cycle α, T clk and t [15]. In fact, the models of PBTI and NBTI are similar to each other.…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

“…In fact, the models of PBTI and NBTI are similar to each other. The BTI effect on V th can be calculated as follows [15],…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

“…where A is a function-dependent factor of the temperature, n is a constant depending on the fabrication process (n = 1/6 or n = 1/4 based on the diffusion type [14]), Y is the duty cycle and t is the total time (transistor age) [15]. In this paper, we define the duty cycle of a transistor as the ratio between the stress time to the total time, which also can be defined by signal probability (SP).…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

“…In this paper, we define the duty cycle of a transistor as the ratio between the stress time to the total time, which also can be defined by signal probability (SP). To further verify the accuracy of this model, we have compared the results of our modeling and the experimental data collected by [15] for the TSMC45-nm technology node. Both data have shown very good matching.…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

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Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

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Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

“…In fact, the models of PBTI and NBTI are similar to each other. The BTI effect on V th can be calculated as follows [15],…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

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Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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“…This Vth drift strongly depends on the amount of time during which a PMOS transistor is stressed. On the other hand, when the stress condition is relaxed, the aging can be recovered partially, and the Vth decreases toward the nominal value [5], [6]. In SRAMs, the value dependence of NBTI is weaker than in logic circuits: given the symmetric structure of a 6T-SRAM cell, one PMOS is always under stress as long as it stores any value so the SRAM cell structure degrades continually [39], [23].…”

Section: Introductionmentioning

confidence: 99%

ARGO: Aging-aware GPGPU register file allocation

Namaki-Shoushtari¹,

Rahimi²,

Dutt³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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State-of-the-art general-purpose graphic processing units (GPGPUs) implemented in nanoscale CMOS technologies offer very high computational throughput for highly-parallel applications using hundreds of integrated on-chip resources. These resources are stressed during application execution, subjecting them to degradation mechanisms such as negative bias temperature instability (NBTI) that adversely affect their reliability. To support highly parallel execution, GPGPUs contain large register files (RFs) that are among the most highly stressed GPGPU components; however we observe heavy underutilization of RFs (on average only 46%) for typical general-purpose kernels. We present ARGO, an Aging-awaRe GPGPU RF allOcator that opportunistically exploits this RF underutilization by distributing the stress throughout RF. ARGO achieves proper leveling of RF banks through deliberated power-gating of stressful banks. We demonstrate our technique on the AMD Evergreen GPGPU architecture and show that ARGO improves the NBTI-induced threshold voltage degradation by up to 43% (on average 27%), that yields improving RFs static noise margin up to 46% (on average 30%). Furthermore, we estimate a simultaneous reduction in leakage power of 54% by providing sleep states for unused banks.

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Design of improved‐reliability nanocircuits with mixed NBTI‐ and HCI‐aware gate‐sizing formulation

Amini‐sheshdeh

Nabavi

2013

IEEJ Transactions Elec Engng

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Negative bias temperature instability (NBTI) and hot carrier injection (HCI) are two important processes of reliability concern in nano-scale integrated circuits. A circuit-level design technique to combat NBTI degradation is gate oversizing. This paper presents a new technique based on PMOS and NMOS resistance variation for the NBTI-and HCI-aware gate-sizing problem for the first time. In this technique, the area of the circuit is minimized with constraints on degraded delay due to NBTI and HCI and the transitor size. Expreimental results for several gates and ISCAS'85 benchmark circuits show that this technique imposes an area overhead of less than 1% with respect to baseline design in most cases. Zhila Amini (Non-member) received the B.Sc. degree from Sharif University, Tehran, Iran, in 2004, and the M.Sc. degree from Tarbiat Modares University (TMU), Tehran, in 2006, both in electrical engineering. Currently, she is pursuing the Ph.D. degree at TMU. Her research interests include VLSI design and digital electronic and digital CMOS circuit reliability. Abdolreza Nabavi (Non-member) received the B.Sc. and M.Sc. degrees from Tehran University, Tehran, Iran, in 1985 and 1987, respectively, and the Ph.D. degree from McGill University, Canada, in 1993, all in electrical engineering. Since 1993, he has been with Faculty of Electrical and Computer Engineering, Tarbiat Modares University, Tehran. His research interests include RFIC design with emphasis on ultrawide-band and millimeter-wave systems, and low-power analog and digital integrated circuits.

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The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Cited by 245 publications

References 21 publications

Optimally Fortifying Logic Reliability through Criticality Ranking

Optimally Fortifying Logic Reliability through Criticality Ranking

ARGO: Aging-aware GPGPU register file allocation

Design of improved‐reliability nanocircuits with mixed NBTI‐ and HCI‐aware gate‐sizing formulation

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