The Impact of Deep Ni Salicidation and$hboxNH_3$Plasma Treatment on Nano-SOI FinFETs

You, Hsin-Chiang; Kuo, Po-Yi; Ko, Fu‐Hsiang; Chao, Tien−Sheng; Lei, Tan Fu

doi:10.1109/led.2006.882519

Cited by 47 publications

(16 citation statements)

References 8 publications

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“…These results indicate the necessity for reduction of the sidewall interface state density to enhance the performance of narrow width FinFETs. Recently, it has been demonstrated that after NH 3 plasma treatment of nano-SOI FinFETs, the leakage current is suppressed dramatically [20].…”

Section: Resultsmentioning

confidence: 99%

Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

Tsormpatzoglou

Dimitriadis

Mouis

et al. 2009

Solid-State Electronics

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Section: Resultsmentioning

confidence: 99%

Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

Tsormpatzoglou

Dimitriadis

Mouis

et al. 2009

Solid-State Electronics

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“…A suitable plasma treatment can improve the electrical characteristics of TFT devices due to the generation of H atoms in NH 3 plasma, which effectively passivates defects in poly-Si TFTs. 21,22 The sintering process has also long been used in the fabrication of semiconductor devices for reducing the contact resistance between the metal and the semiconductor. Sintering was performed in atmospheric pressure N 2 ambient diluted z E-mail: kuopoyi.ee91g@gmail.com with 5% H 2 .…”

Section: Methodsmentioning

confidence: 99%

The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate Structure

Kuo¹,

Huang²,

Lue³

et al. 2010

J. Electrochem. Soc.

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n-and p-channel poly-Si thin-film transistors with fully Ni-self-aligned silicided ͑fully Ni-salicided͒ source/drain ͑S/D͒ and gate structure ͑n-and p-channel FUSA-TFTs͒ have been successfully fabricated on a 40 nm thick channel layer. The conventional poly-Si gate is replaced by the fully Ni-silicided gate, and the parasitic S/D resistance of the FUSA-TFTs is significantly reduced by the fully Ni-silicided S/D structure. The fully Ni-salicidation process is executed at a low temperature of 500°C for a short rapid thermal annealing time. Experimental results show that the FUSA-TFTs give increased on/off current ratio, improved subthreshold characteristics, less threshold voltage roll-off, lower parasitic S/D resistance, higher gate capacitance, and larger field-effect mobility than conventional TFTs. The FUSA-TFTs effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FUSA-TFTs are suitable for three-dimensional integration applications and high performance driver circuits in the active-matrix liquid crystal displays.Polycrystalline silicon thin-film transistors ͑poly-Si TFTs͒ have been widely used in many potential applications including threedimensional ͑3D͒ integration high density flash memories, pixel driving elements in active-matrix organic light emitting diodes and integrated peripheral driving circuits, and addressing elements of active-matrix liquid crystal displays ͑AMLCDs͒. 1-4 However, the output characteristics exhibit an anomalous increase in current in the saturation regime, often called the "kink" effect by analogy with silicon-on-insulator ͑SOI͒ devices. 5-7 This phenomenon can be attributed to the floating-body effect 8 and avalanche multiplication enhanced by grain boundary traps, 6 particularly in n-channel TFTs. With increasing drain voltage, the added drain current enhances impact ionization and the parasitic bipolar junction transistor ͑BJT͒ effect, which leads to a premature breakdown in return. 8 In the floating-body thin-film devices, the improved parasitic BJT effect can be achieved by using deep salicidation and a fully silicided source/drain ͑S/D͒ structure. 9,10 Due to low hole field-effect mobility, p-channel TFTs have a lower on-state current than n-channel TFTs. Nevertheless, p-channel TFTs have advantages, such as a lower off-state leakage current, slighter floating-body and kink effects, a weaker drain impact ionization, and a higher hot carrier reliability. In addition, thin-channel poly-Si TFTs have better device characteristics such as a small leakage current and a suppressed floating-body effect than thick-channel poly-Si TFTs. 11 However, a thin-channel film also leads to increased parasitic S/D resistance. Parasitic S/D resistances become an increasingly serious issue for thin-channel poly-Si TFTs and SOI devices. Several methods such as self-aligned silicide, selective tungsten-clad and metal-replaced junction technology have been proposed to reduce parasitic S/D resistance in thin-channel SOI devices an...

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“…To overcome these disadvantages, various charge-trapping materials as well as blocking and tunneling materials were extensively investigated. Among which, high- k materials including thin films and their nanocrystals, for example HfO 2 , TiO 2 , and ZrO 2 , have been proposed as the charge-trapping layer in the CTM devices to achieve better storage performance and retention characteristics [4–7]. In these high- k dielectrics, oxygen vacancy is verified as the main origin of the defects in the film [8].…”

Section: Introductionmentioning

confidence: 99%

Electronic Structure and Charge-Trapping Characteristics of the Al2O3-TiAlO-SiO2 Gate Stack for Nonvolatile Memory Applications

Yang

Tang

et al. 2017

Nanoscale Res Lett

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In this work, high-k composite TiAlO film has been investigated as charge-trapping material for nonvolatile memory applications. The annealing formed Al2O3-TiAlO-SiO2 dielectric stack demonstrates significant memory effects and excellent reliability properties. The memory device exhibits a large memory window of ~2.6 V under ±8 V sweeping voltage, and it shows only ~14% charge loss after more than 10 years’ retention, indicating excellent charge retention properties. The electronic structures of the Al2O3-TiAlO-SiO2 have been studied by X-ray photoelectron spectroscopy measurements, and it reveals that the quantum well and the defect traps in TiAlO film can provide a >1.8 eV deep barrier for charge confinement in the TiAlO layer. The mixing between Al2O3 and TiO2 can increase the defects related to the under-coordinated Ti3+ atoms, thereby enhancing the charge-trapping efficiency of the device. Our work implies that high-k TiAlO composite film is promising for applications in future nonvolatile charge-trapping memories.

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The Impact of Deep Ni Salicidation and$hboxNH_3$Plasma Treatment on Nano-SOI FinFETs

Cited by 47 publications

References 8 publications

Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate Structure

Electronic Structure and Charge-Trapping Characteristics of the Al2O3-TiAlO-SiO2 Gate Stack for Nonvolatile Memory Applications

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