The EPFL Logic Synthesis Libraries

Soeken, Mathias; Riener, Heinz; Haaswijk, Winston; Testa, Eleonora; Schmitt, Bruno; Meuli, Giulia; Mozafari, Fereshte; Lee, Siang-Yun; Calvino, Alessandro Tempia; Marakkalage, Dewmini Sudara; Micheli, Giovanni De

doi:10.48550/arxiv.1805.05121

Cited by 14 publications

(14 citation statements)

References 11 publications

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“…In this section, we present experimental results using different combinations of technology assumptions discussed in Section 3. The irredundant buffer insertion and chunked movement algorithms are implemented in C++-17 as part of the EPFL logic synthesis library mockturtle 1 [8]. As discussed in Section 2.1, the intrinsic logic gate in the AQFP technology is the majority-3 gate, majority-inverter graphs (MIGs) [1] are used as the data structure for (unmapped) networks in our experiments.…”

Section: Resultsmentioning

confidence: 99%

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits

Lee,

Riener,

De Micheli

2021

Preprint

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The adiabatic quantum-flux parametron (AQFP) is a promising energy-efficient superconducting technology. Before technology mapping, additional buffer and splitter cells need to be inserted into AQFP circuits to fulfill two special constraints: (1) Input signals to a logic gate need to arrive at the same time, thus shorter paths need to be delayed with buffers. (2) The output signal of a logic gate has to be actively branched with splitters if it drives multiple fanouts. Buffers and splitters largely increase the area and delay in AQFP circuits. Naïve buffer and splitter insertion and lightweight optimization using retiming techniques have been used in related works, and it is not clear how much space there is for further optimization. In this paper, we develop (a) a linear-time algorithm to insert buffers and splitters irredundantly, and (b) optimization methods by scheduling and by moving groups of gates, called chunks, together. Experimental results show a reduction of up to 39% on buffer and splitter cost. Moreover, as the technology is still developing and assumptions on the physical constraints are not clear yet, we also discuss the impacts of different assumptions with experimental results to motivate future research on AQFP register design.

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Section: Resultsmentioning

confidence: 99%

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits

Lee,

Riener,

De Micheli

2021

Preprint

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“…We use various arithmetic and random-control functions from [1] as well as cryptographic functions and IEEE floating-point operations [4] as benchmarks for our algorithm. Our algorithm has been implemented in C++ on top of the EPFL logic synthesis libraries [51]. All experiments were run on a Microsoft Azure virtual machine, on a general purpose Standard D8s v3 size configuration, running on an Intel Xeon Platinum 8171M 2.40GHz CPU with 32 GiB memory and Ubuntu 18.04.…”

Section: Resultsmentioning

confidence: 99%

Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks

Häner¹,

Soeken²

2020

Preprint

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The multiplicative depth of a logic network over the gate basis {∧, ⊕, ¬} is the largest number of ∧ gates on any path from a primary input to a primary output in the network. We describe a dynamic programming based logic synthesis algorithm to reduce the multiplicative depth in logic networks. It makes use of cut enumeration, tree balancing, and exclusive sum-of-products (ESOP) representations. Our algorithm has applications to cryptography and quantum computing, as a reduction in the multiplicative depth directly translates to a lower T -depth of the corresponding quantum circuit. Our experimental results show improvements in T -depth over state-of-the-art methods and over several hand-optimized quantum circuits for instances of AES, SHA, and floating-point arithmetic.

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“…We have implemented the algorithm using the EPFL logic synthesis libraries [27]. In our experiments, we used the exact synthesis algorithms to verify known multiplicative complexities for Boolean functions with up to 6 variables [9], [20].…”

Section: Resultsmentioning

confidence: 99%

Determining the Multiplicative Complexity of Boolean Functions using SAT

Soeken

2020

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We present a constructive SAT-based algorithm to determine the multiplicative complexity of a Boolean function, i.e., the smallest number of AND gates in any logic network that consists of 2-input AND gates, 2-input XOR gates, and inverters. In order to speed-up solving time, we make use of several symmetry breaking constraints; these exploit properties of XAGs that may be useful beyond the proposed SAT-based algorithm. We further propose a heuristic post-optimization algorithm to reduce the number of XOR gates once the optimum number of AND gates has been obtained, which also makes use of SAT solvers. Our algorithm is capable to find all optimum XAGs for representatives of all 5-input affine-equivalent classes, and for a set of frequently occurring 6-input functions.

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The EPFL Logic Synthesis Libraries

Cited by 14 publications

References 11 publications

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits

Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks

Determining the Multiplicative Complexity of Boolean Functions using SAT

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